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AD660AN-AD660AR-AD660BR
Monolithic 16-Bit Serial/Byte DACPORT
FUNCTIONAL BLOCK DIAGRAMREV.A
Monolithic 16-Bit
Serial/Byte DACPORT
FEATURES
Complete 16-Bit D/A Function
On-Chip Output Amplifier
On-Chip Buried Zener Voltage Reference61 LSB Integral Linearity
15-Bit Monotonic over Temperature
Microprocessor Compatible
Serial or Byte Input
Double Buffered Latches
Fast (40 ns) Write Pulse
Asynchronous Clear (to 0 V) Function
Serial Output Pin Facilitates Daisy Chaining
Unipolar or Bipolar Output
Low Glitch: 15 nV-s
Low THD+N: 0.009%
PRODUCT DESCRIPTIONThe AD660 DACPORT is a complete 16-bit monolithic D/A
converter with an on-board voltage reference, double buffered
latches and output amplifier. It is manufactured on Analog De-
vices’ BiMOS II process. This process allows the fabrication of
low power CMOS logic functions on the same chip as high pre-
cision bipolar linear circuitry.
The AD660’s architecture ensures 15-bit monotonicity over
time and temperature. Integral and differential nonlinearity is
maintained at ±0.003% max. The on-chip output amplifier pro-
vides a voltage output settling time of 10 μs to within 1/2 LSB
for a full-scale step.
The AD660 has an extremely flexible digital interface. Data can
be loaded into the AD660 in serial mode or as two 8-bit bytes.
This is made possible by two digital input pins which have dual
functions. The serial mode input format is pin selectable to be
MSB or LSB first. The serial output pin allows the user to daisy
chain several AD660s by shifting the data through the input
latch into the next DAC thus minimizing the number of control
lines required to SIN, CS and LDAC. The byte mode input for-
mat is also flexible in that the high byte or low byte data can be
loaded first. The double buffered latch structure eliminates data
skew errors and provides for simultaneous updating of DACs in
a multi-DAC system.
The AD660 is available in five grades. AN and BN versions are
specified from –40°C to +85°C and are packaged in a 24-pin
300 mil plastic DIP. AR and BR versions are also specified from
–40°C to +85°C and are packaged in a 24-pin SOIC. The SQ
version is packaged in a 24-pin 300 mil cerdip package and is
also available compliant to MIL-STD-883. Refer to the AD660/
883B data sheet for specifications and test conditions.
DACPORT is a registered trademark of Analog Devices, Inc.
PRODUCT HIGHLIGHTS1. The AD660 is a complete 16-bit DAC, with a voltage refer-
ence, double buffered latches and output amplifier on a sin-
gle chip.
2. The internal buried Zener reference is laser trimmed to
10.000 volts with a ±0.1% maximum error and a tempera-
ture drift performance of ±15 ppm/°C. The reference is
available for external applications.
3. The output range of the AD660 is pin programmable and can
be set to provide a unipolar output range of 0 V to +10 V or
a bipolar output range of –10 V to +10 V. No external com-
ponents are required.
4. The AD660 is both dc and ac specified. DC specifications
include ±1 LSB INL and ±1 LSB DNL errors. AC specifi-
cations include 0.009% THD+N and 83 dB SNR.
5. The double buffered latches on the AD660 eliminate data
skew errors and allow simultaneous updating of DACs in
multi-DAC applications.
6. The CLEAR function can asynchronously set the output to
0 V regardless of whether the DAC is in unipolar or bipolar
mode.
7. The output amplifier settles within 10 μs to ±1/2 LSB for a
full-scale step and within 2.5 μs for a 1 LSB step over tem-
perature. The output glitch is typically 15 nV-s when a full-
scale step is loaded.
AD660–SPECIFICATIONS(TA = +258C, VCC = +15 V, VEE = –15 V, VLL = +5 V unless otherwise noted)TRANSFER FUNCTION CHARACTERISTICS
REFERENCE OUTPUT
OUTPUT CHARACTERISTICS
POWER SUPPLIES
TEMPERATURE RANGE
NOTESFor 16-bit resolution, 1 LSB = 0.0015% of FSR. For 15-bit resolution, 1 LSB = 0.003% of FSR. For 14-bit resolution, 1 LSB = 0.006% of FSR. FSR stands for
Full-Scale Range and is 10 V in a Unipolar Mode and 20 V in Bipolar Mode.Gain error and gain drift are measured using the internal reference. The internal reference is the main contributor to gain drift. If lower gain drift is required, the
AD660 can be used with a precision external reference such as the AD587, AD586 or AD688.Gain Error is measured with fixed 50 Ω resistors as shown in the Application section. Eliminating these resistors increases the gain error by 0.25% of FSR (Unipolar
(With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise
Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested.
TMIN ≤ TA ≤ TMAX, VCC = +15 V, VEE = –15 V, VLL = +5 V except where noted.)Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD660 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*VCC to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +17.0 V
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17.0 V
VLL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±1 V
Digital Inputs (Pins 5 through 23) to DGND . . . . . .–1.0 V to
+7.0 V
REF IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .±10.5 V
Span/Bipolar Offset to AGND . . . . . . . . . . . . . . . . . . .±10.5 V
Ref Out, VOUT . . . . . . .Indefinite Short to AGND, DGND,
VCC, VEE, and VLL
Power Dissipation (Any Package)
To +60°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000 mW
Derates above +60°C . . . . . . . . . . . . . . . . . . . .8.7 mW/°C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range
(Soldering10sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
PIN CONFIGURATION
DB7, 15OUT
SPAN,
BIPOLAR OFFSET OUT
AGND
REF OUT
REF IN
LDAC
DGNDEECCLL
HBE
SER
CLR
DB6, 14
DB5, 13
DB4, 12
DB3, 11
DB2, 10
DB0, 8, SIN
DB1, 9, MSB/LSB
LBE, UNI/BIP CLEAR
AD660
ORDERING GUIDEAD660AN
AD660AR
AD660BN
AD660BR
AD660SQ
*N = Plastic DIP; Q = Cerdip; R = SOIC.
**Refer to AD660/883B military data sheet.
TIMING CHARACTERISTICSVCC = +15 V, VEE = –15 V, VLL = +5 V, VHI = 2.4 V, VLO = 0.4 V(Figure la)
Specifications subject to change without notice.
BIT 0–7
HBE OR
LBE
LDAC
BIT0SER
LDAC
BIT1Figure 1b.AD660 Serial Load Timing
CLR
LBEFigure 1c.Asynchronous Clear to Bipolar or Unipolar Zero
BIT0
SER
BIT 1
(MSB/LSB)SERIAL
OUTFigure 1d.Serial Out Timing
DEFINITIONS OF SPECIFICATIONSINTEGRAL NONLINEARITY: Analog Devices defines
integral nonlinearity as the maximum deviation of the actual,
adjusted DAC output from the ideal analog output (a straight
line drawn from 0 to FS–1 LSB) for any bit combination. This
is also referred to as relative accuracy.
DIFFERENTIAL NONLINEARITY: Differential nonlinearity
is the measure of the change in the analog output, normalized to
full scale, associated with a 1 LSB change in the digital input
code. Monotonic behavior requires that the differential linearity
error be greater than or equal to –1 LSB over the temperature
range of interest.
MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs with
the result that the output will always be a single-valued function
of the input.
GAIN ERROR: Gain error is a measure of the output error be-
tween an ideal DAC and the actual device output with all 1s
BIPOLAR ZERO ERROR: When the AD660 is connected for
bipolar output and 10 . . . 000 is loaded in the DAC, the devia-
tion of the analog output from the ideal midscale value of 0 V is
called the bipolar zero error.
DRIFT: Drift is the change in a parameter (such as gain, offset
and bipolar zero) over a specified temperature range. The drift
temperature coefficient, specified in ppm/°C, is calculated by
measuring the parameter at TMIN, 25°C and TMAX and dividing
the change in the parameter by the corresponding temperature
change.
TOTAL HARMONIC DISTORTION + NOISE: Total har-
monic distortion + noise (THD+N) is defined as the ratio of the
square root of the sum of the squares of the values of the har-
monics and noise to the value of the fundamental input fre-
quency. It is usually expressed in percent (%).
THD+N is a measure of the magnitude and distribution of lin-
earity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depend-
AD660SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is de-
fined as the ratio of the amplitude of the output when a full-
scale signal is present to the output with no signal present. This
is measured in dB.
DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the
amount of charge injected from the digital inputs to the analog
output when the inputs change state. This is measured at half
scale when the DAC switches around the MSB and as many
as possible switches change state, i.e., from 011 . . . 111 to
100 . . . 000.
DIGITAL FEEDTHROUGH: When the DAC is not selected
(i.e., CS is held high), high frequency logic activity on the digi-
tal inputs is capacitively coupled through the device to show up
as noise on the VOUT pin. This noise is digital feedthrough.
THEORY OF OPERATIONThe AD660 uses an array of bipolar current sources with MOS
current steering switches to develop a current proportional to
the applied digital word, ranging from 0 to 2 mA. A segmented
architecture is used, where the most significant four data bits are
thermometer decoded to drive 15 equal current sources. The
lesser bits are scaled using a R-2R ladder, then applied together
with the segmented sources to the summing node of the output
amplifier. The internal span/bipolar offset resistor can be con-
nected to the DAC output to provide a 0 V to +10 V span, or it
can be connected to the reference input to provide a –10 V to
+10 V span.
SIN/
DB0DB7OUT
SPAN/
BIP
OFFSETOUT
AGND
REF OUT
REF IN
LDAC
SER
DGND–VEE+VCC+VLL234
LBECS
HBE
CLR
MSB/LSB/
DB1
UNI/BIP CLR/Figure 2.AD660 Functional Block Diagram
ANALOG CIRCUIT CONNECTIONSInternal scaling resistors provided in the AD660 may be con-
nected to produce a unipolar output range of 0 V to +10 V or a
bipolar output range of –10 V to +10 V. Gain and offset drift
are minimized in the AD660 because of the thermal tracking of
the scaling resistors with other device components.
UNIPOLAR CONFIGURATIONThe configuration shown in Figure 3a will provide a unipolar
0 V to +10 V output range. In this mode, 50 Ω resistors are tied
between the span/bipolar offset terminal (Pin 22) and VOUT
(Pin 21), and between REF OUT (Pin 24) and REF IN (Pin
23). It is possible to use the AD660 without any external compo-
nents by tying Pin 24 directly to Pin 23 and Pin 22 directly to
Pin 21. Eliminating these resistors will increase the gain error by
0.25% of FSR.
Figure 3a.0 V to +10 V Unipolar Voltage Output
If it is desired to adjust the gain and offset errors to zero, this can
be accomplished using the circuit shown in Figure 3b. The ad-
justment procedure is as follows:
STEP 1 . . . ZERO ADJUST
Turn all bits OFF and adjust zero trimmer, R4, until the output
reads 0.000000 volts (1 LSB = 153 μV).
STEP 2 . . . GAIN ADJUST
Turn all bits ON and adjust gain trimmer, R1, until the output is
9.999847 volts. (Full scale is adjusted to 1 LSB less than the
nominal full scale of 10.000000 volts).
Figure 3b.0 V to +10 V Unipolar Voltage Output with Gain
and Offset Adjustment
