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AD654
Low Cost Monolithic Voltage-to-Frequency Converter
REV.B
Low Cost Monolithic
Voltage-to-Frequency Converter
FEATURES
Low Cost
Single or Dual Supply, 5 V to 36 V, 65 V to 618 V
Full-Scale Frequency Up to 500 kHz
Minimum Number of External Components Needed
Versatile Input Amplifier
Positive or Negative Voltage Modes
Negative Current Mode
High Input Impedance, Low Drift
Low Power: 2.0 mA Quiescent Current
Low Offset: 1 mV
PRODUCT DESCRIPTIONThe AD654 is a monolithic V/F converter consisting of an input
amplifier, a precision oscillator system, and a high current output
stage. A single RC network is all that is required to set up any
full scale (FS) frequency up to 500 kHz and any FS input voltage
up to –30 V. Linearity error is only 0.03% for a 250 kHz FS,
and operation is guaranteed over an 80 dB dynamic range. The
overall temperature coefficient (excluding the effects of external
components) is typically –50 ppm/°C. The AD654 operates from
a single supply of 5 V to 36 V and consumes only 2.0 mA quies-
cent current.
The low drift (4 mV/°C typ) input amplifier allows operation
directly from small signals such as thermocouples or strain gauges
while offering a high (250 MW) input resistance. Unlike most
V/F converters, the AD654 provides a square-wave output, and
can drive up to 12 TTL loads, optocouplers, long cables, or
similar loads.
PRODUCT HIGHLIGHTSPackaged in both an 8-lead mini-DIP and an 8-lead SOIC
package, the AD654 is a complete V/F converter requiring
only an RC timing network to set the desired full-scale fre-
quency and a selectable pull-up resistor for the open-collector
output stage. Any full scale input voltage range from 100 mV
to 10 volts (or greater, depending on +VS) can be accommo-
dated by proper selection of the timing resistor. The full-
scale frequency is then set by the timing capacitor from the
simple relationship, f = V/10 RC.A minimum number of low cost external components are
necessary. A single RC network is all that is required to set
up any full scale frequency up to 500 kHz and any full-scale
input voltage up to –30 V.Plastic packaging allows low cost implementation of the
standard VFC applications: A/D conversion, isolated signal
transmission, F/V conversion, phase-locked loops, and tuning
switched-capacitor filters.Power supply requirements are minimal; only 2.0 mA of
quiescent current is drawn from the single positive supply
from 4.5 volts to 36 volts. In this mode, positive inputs can
vary from 0 volts (ground) to (+VS –4) volts. Negative inputs
can easily be connected for below ground operation.
5. The versatile open-collector output stage can sink more than
10 mA with a saturation voltage less than 0.4 volts. The Logic
Common terminal can be connected to any level between
ground (or –VS) and 4 volts below +VS. This allows easy
direct interface to any logic family with either positive or
negative logic levels.
FUNCTIONAL BLOCK DIAGRAM
AD654–SPECIFICATIONS
(TA = +258C and VS (total) = 5 V to 16.5 V, unless otherwise noted. All testing done
@ VS = +5 V.)TEMPERATURE RANGE
NOTESAt fMAX = 250 kHz; RT = 1 kW, CT = 390 pF, IIN = 0 mA–1 mA.At fMAX = 500 kHz; RT = 1 kW, CT = 200 pF, IIN = 0 mA–1 mA.The sink current is the amount of current that can flow into Pin 1 of the AD654 while maintaining a maximum voltage of 0.4 V between Pin 1 and Logic Common.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGTotal Supply Voltage +VS to –VS . . . . . . . . . . . . . . . . . . .36 V
Maximum Input Voltage
(Pins 3, 4) to –VS . . . . . . . . . . . . . . . . . . . .–300 mV to +VS
Maximum Output Current
Instantaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Sustained . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 mA
Logic Common to –VS . . . . . . . . . . . . . . .–500 mV to (+VS –4)
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
ORDERING GUIDE
AD654
CIRCUIT OPERATIONThe AD654’s block diagram appears in Figure 1. A versatile
operational amplifier serves as the input stage; its purpose is to
convert and scale the input voltage signal to a drive current in the
NPN follower. Optimum performance is achieved when, at the
full-scale input voltage, a 1 mA drive current is delivered to the
current-to-frequency converter (an astable multivibrator). The
drive current provides both the bias levels and the charging current
to the externally connected timing capacitor. This “adaptive” bias
scheme allows the oscillator to provide low nonlinearity over
the entire current input range of 100 nA to 2 mA. The square
wave oscillator output goes to the output driver which provides
a floating base drive to the NPN power transistor. This floating
drive allows the logic interface to be referenced to a level other
than –VS.
Figure 1.Standard V-F Connection for Positive Input
Voltages
V/F CONNECTION FOR POSITIVE INPUT VOLTAGESIn the connection scheme of Figure 1, the input amplifier presents
a very high (250 MW) impedance to the input voltage, which
is converted into the proper drive current by the scaling resistors
at Pin 3. Resistors R1 and R2 are selected to provide a 1 mA
full-scale current with enough trim range to accommodate the
AD654’s 10% FS error and the components’ tolerances. Full-
scale currents other than 1 mA can be chosen, but linearity will
be reduced; 2 mA is the maximum allowable drive. The AD654’s
positive input voltage range spans from –VS (ground in sink supply
operation) to four volts below the positive supply. Power sup-
ply rejection degrades as the input exceeds (+VS – 3.75 V) and at
(+VS – 3.5 V) the output frequency goes to zero.
As indicated by the scaling relationship in Figure 1, a 0.01 mF
timing capacitor will give a 10 kHz full-scale frequency, and
0.001 mF will give 100 kHz with a 1 mA drive current. Good V/F
linearity requires the use of a capacitor with low dielectric
absorption (DA), while the most stable operation over tempera-
ture calls for a component having a small tempco. Polystyrene,
polypropylene, or Teflon* capacitors are preferred for tempco and
dielectric absorption; other types will degrade linearity. The
capacitor should be wired very close to the AD654. In Figure 1,
Schottky diode CR1 (MBD101) prevents logic common from
dropping more than 500 mV below –VS. This diode is not
required if –VS is equal to logic common.
V/F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE
OR CURRENTThe AD654 can accommodate a wide range of negative input
voltages with proper selection of the scaling resistor, as indicated
in Figure 2. This connection, unlike the buffered positive con-
nection, is not high impedance because the signal source must
supply the 1 mA FS drive current. However, large negative volt-
ages beyond the supply can be handled easily by modifying the
scaling resistors appropriately. If the input is a true current source,
R1 and R2 are not used. Again, diode CR1 prevents latch-up by
insuring Logic Common does not drop more than 500 mV below
–VS. The clamp diode (MBD101) protects the AD654 input
from “below –VS” inputs.
Figure 2. V-F Connections for Negative Input Voltages or
Current
OFFSET CALIBRATIONIn theory, two adjustments calibrate a V/F: scale and offset. In
practice, most applications find the AD654’s 1 mV max voltage
offset sufficiently low to forgo offset calibration. However, the
input amplifier’s 30 nA (typ) bias currents will generate an offset
due to the difference in dc sound resistance between the input
terminals. This offset can be substantial for large values of RT =
R1 + R2 and will vary as the bias currents drift over temperature.
Therefore, to maintain the AD654’s low offset, the application may
require balancing the dc source resistances at the inputs (Pins
3 and 4).
For positive inputs, this is accomplished by adding a compensation
resistor nominally equal to RT in series with the input as shown
in Figure 3a. This limits the offset to the product of the 30 nA
bias current and the mismatch between the source resistance RT
and RCOMP. A second, smaller offset arises from the inputs’ 5 nA
offset current flowing through the source resistance RT or RCOMP.
For negative input voltage and current connections, the compensa-
tion resistor is added at Pin 4 as shown in Figure 3b in lieu of
grounding the pin directly. For both positive and negative inputs,
the use of RCOMP may lead to noise coupling at Pin 4 and should
therefore be bypassed for lowest noise operation.
VIN
RCOMP
(OPTIONAL)
(OPTIONAL)VIN
RCOMPFigure 3b.Bias Current Compensation—Negative Inputs
If the AD654’s 1 mV offset voltage must be trimmed, the trim
must be performed external to the device. Figure 3c shows an
optional connection for positive inputs in which ROFF1 and
ROFF2 add a variable resistance in series with RT. A variable
source of –0.6 V applied to ROFF1 then adjusts the offset –1 mV.
Similarly, a –0.6 V variable source is applied to ROFF in Fig-
ure 3d to trim offset for negative inputs. The –0.6 V bipolar
source could simply be an AD589 reference connected as shown
in Figure 3e.
VIN
10kV
5kV8.25kV
ROFF2
20V
ROFF1
10kV60.6V
Figure 3c. Offset Trim Positive Input (10 V FS)
VIN
10kV
5kV8.25kV
ROFF
5.6MV60.6V
Figure 3d. Offset Trim Negative Input (–10 V FS)
+5V60.6V
AD589
10kV
10kV
10kV
–5VFigure 3e.Offset Trim Bias Network
FULL-SCALE CALIBRATIONFull-scale trim is the calibration of the circuit to produce the
desired output frequency with a full-scale input applied. In most
cases this is accomplished by adjusting the scaling resistor RT.
Precise calibration of the AD654 requires the use of an accurate
voltage standard set to the desired FS value and an accurate
frequency meter. A scope is handy for monitoring output wave-
shape. Verification of converter linearity requires the use of a
linearity, it is unnecessary for the end-user to perform this tedious
and time consuming test on a routine basis.
Sufficient FS calibration trim range must be provided to accom-
modate the worst-case sum of all major scaling errors. This
includes the AD654’s 10% full-scale error, the tolerance of the
fixed scaling resistor, and the tolerance of the timing capacitor.
Therefore, with a resistor tolerance of 1% and a capacitor tolerance
of 5%, the fixed part of the scaling resistor should be a maximum
of 84% of nominal, with the variable portion selected to allow
116% of the nominal.
If the input is in the form of a negative current source, the scaling
resistor is no longer required, eliminating the capability of trim-
ming FS frequency in this fashion. Since it is usually not practical
to smoothly vary the capacitance for trimming purposes, an
alternative scheme such as the one shown in Figure 4 is needed.
Designed for a FS of 1 mA, this circuit divides the input into two
Figure 4.Current Source FS Trim
and flowing into Pin 3; it constitutes the signal current IT to be
converted. The second path, through another 100 W resistor R2,
carries the same nominal current. Two equal valued resistors
offer the best overall stability, and should be either 1% discrete
film units, or a pair from a common array.
Since the 1 mA FS input current is divided into two 500 mA legs
(one to ground and one to Pin 3), the total input signal current
(IS) is divided by a factor of two in this network. To achieve the
same conversion scale factor, CT must be reduced by a factor of
two. This results in a transfer unique to this hookup:
For calibration purposes, resistors R3 and R4 are added to the
network, allowing a –15% trim of scale factor with the values
shown. By varying R4’s value the trim range can be modified to
accommodate wider tolerance components or perhaps the cali-
bration tolerance on a current output transducer such as the
AD592 temperature sensor. Although the values of R1–R4 shown
are valid for 1 mA FS signals only, they can be scaled upward
proportionately for lower FS currents. For instance, they should
be increased by a factor of ten for a FS current of 100 mA.
In addition to the offsets generated by the input amplifier’s bias
and offset currents, an offset voltage induced parasitic current
arises from the current fork input network. These effects are
AD654and insure the supply, source and load are appropriate. If provision
is made to trim offset, begin by setting the input to 1/10,000 of
full scale. Adjust the offset pot until the output is 1/10,000 of
full scale (for example, 25 Hz for a FS of 250 kHz). This is most
easily accomplished using a frequency meter connected to the
output. The FS input should then be applied and the gain pot
should be adjusted until the desired FS frequency is indicated.
INPUT PROTECTIONThe AD654 was designed to be used with a minimum of additional
hardware. However, the successful application of a precision IC
involves a good understanding of possible pitfalls and the use of
suitable precautions. Thus +VIN and RT pins should not be driven
more than 300 mV below –VS. Likewise, Logic Common should
not drop more than 500 mV below –VS. This would cause inter-
nal junctions to conduct, possibly damaging the IC. In addition
to the diode shown in Figures 1 and 2 protecting Logic Common,
a second Schottky diode (MBD101) can protect the AD654’s
inputs from “below –VS’’ inputs as shown in Figure 5. It is also
desirable not to drive +VIN and RT above +VS. In operation, the
converter will exhibit a zero output for inputs above (+VS – 3.5 V).
Also, control currents above 2 mA will increase nonlinearity.
The AD654’s 80 dB dynamic range guarantees operation from a
control current of 1 mA (nominal FS) down to 100 nA (equiva-
lent to 1 mV to 10 V FS). Below 100 nA improper operation of
the oscillator may result, causing a false indication of input
amplitude. In many cases this might be due to short-lived noise
spikes which become added to input. For example, when scaled
to accept an FS input of 1 V, the –80 dB level is only 100 mV, so
when the mean input is only 60 dB below FS (1 mV), noise spikes
of 0.9 mV are sufficient to cause momentary malfunction.
This effect can be minimized by using a simple low-pass filter
ahead of the converter or a guard ring around the RT pin. The
filter can be assembled using the bias current compensation
resistor discussed in the previous section. For an FS of 10 kHz,
a single-pole filter with a time constant of 100 ms will be suitable,
but the optimum configuration will depend on the application
and the type of signal processing. Noise spikes are only likely to
be a cause of error when the input current remains near its mini-
mum value for long periods of time; above 100 nA full integration
of additive input noise occurs. Like the inputs, the capacitor
terminals are sensitive to interference from other signals. The
timing capacitor should be located as close as possible to the
AD654 to minimize signal pickup in the leads. In some cases,
guard rings or shielding may be required.
Figure 5. Input Protection
between the various circuits in the system. Ceramic capacitors
of 0.1 mF to 1.0 mF should be applied between the supply-
voltage pins and analog signal ground for proper bypassing on
the AD654. A proper ground scheme appears in Figure 6.
Figure 6.Proper Ground Scheme
OUTPUT INTERFACING CONSIDERATIONThe output stage’s design allows easy interfacing to all digital logic
families. The output NPN transistor’s emitter and collector are
both uncommitted. The emitter can be tied to any voltage between
–VS and 4 volts below +VS, and the open collector can be pulled
up to a voltage 36 volts above the emitter regardless of +VS. The
high power output stage can sink over 10 mA at a maximum
saturation voltage of 0.4 V. The stage limits the output current
at 25 mA and can handle this limit indefinitely without damag-
ing the device.
NONLINEARITY SPECIFICATIONThe preferred method of specifying nonlinearity error is in terms
of maximum deviation from the ideal relationship after calibrat-
ing the converter at full scale. This error will vary with the full
scale frequency and the mode of operation. The AD654 operates
best at a 150 kHz full-scale frequency with a negative voltage input;
the linearity is typically within 0.05%. Operating at higher fre-
quencies or with positive inputs will degrade the linearity as
indicated in the Specifications Table. Typical linearity at various
temperatures is shown in Figure 7.
FULL-SCALE FREQUENCY – kHz
MAXIMUM NONLINEARITY – %
0.05Figure 7.Typical Nonlinearities at Different Full-Scale
