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AD652AQ-AD652BQ-AD652JP
Monolithic Synchronous Voltage-to-Frequency Converter
FUNCTIONAL BLOCK DIAGRAMREV.B
Monolithic Synchronous
Voltage-to-Frequency Converter
FEATURES
Full-Scale Frequency (Up to 2 MHz) Set by External
System Clock
Extremely Low Linearity Error (0.005% max at 1 MHz
FS, 0.02% max at 2 MHz FS)
No Critical External Components Required
Accurate 5 V Reference Voltage
Low Drift (25 ppm/�C max)
Dual or Single Supply Operation
Voltage or Current Input
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTIONThe AD652 Synchronous Voltage-to-Frequency Converter
(SVFC) is a powerful building block for precision analog-to-
digital conversion, offering typical nonlinearity of 0.002%
(0.005% maximum) at a 100 kHz output frequency. The inher-
ent monotonicity of the transfer function and wide range of
clock frequencies allows the conversion time and resolution to
be optimized for specific applications.
The AD652 uses a variation of the popular charge-balancing
technique to perform the conversion function. The AD652 uses
an external clock to define the full-scale output frequency,
rather than relying on the stability of an external capacitor. The
result is a more stable, more linear transfer function, with sig-
nificant application benefits in both single- and multichannel
systems.
Gain drift is minimized using a precision low drift reference and
low TC on-chip thin-film scaling resistors. Furthermore, the ini-
tial gain error is reduced to less than 0.5% by the use of
laser-wafer-trimming.
The analog and digital sections of the AD652 have been de-
signed to allow operation from a single-ended power source,
simplifying its use with isolated power supplies.
The AD652 is available in five performance grades. The 20-lead
PLCC packaged JP and KP grades are specified for operation
over the 0°C to +70°C commercial temperature range. The
16-lead cerdip-packaged AQ and BQ grades are specified for
operation over the –40°C to +85°C industrial temperature
range, and the AD652SQ is available for operation over the full
–55°C to +125°C extended temperature range.
PRODUCT HIGHLIGHTSThe use of an external clock to set the full-scale frequency
allows the AD652 to achieve linearity and stability far supe-
rior to other monolithic VFCs. By using the same clock to
drive the AD652 and (through a suitable divider) also set the
counting period, conversion accuracy is maintained indepen-
dent of variations in clock frequency.The AD652 Synchronous VFC requires only a single external
component (a noncritical integrator capacitor) for operation.The AD652 includes a buffered, accurate 5 V reference
which is available to the user.The clock input of the AD652 is TTL and CMOS compat-
ible and can also be driven by sources referred to the negative
power supply. The flexible open-collector output stage pro-
vides sufficient current sinking capability for TTL and CMOS
logic, as well as for optical couplers and pulse transformers.
A capacitor-programmable one-shot is provided for selection
of optimum output pulse width for power reduction.The AD652 can also be configured for use as a synchronous
F/V converter for isolated analog signal transmission.The AD652 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD652/883B data sheet for detailed
specifications.
AD652–SPECIFICATIONS(typical @ TA = +25�C, VS = �15 V, unless otherwise noted)COMPARATOR
CLOCK INPUT
AD652REFERENCE OUTPUT
POWER SUPPLY
NOTESReferred to internal VREF. In PLCC package, tested on 10 V input range only.
Specifications in boldface are 100% tested at final test and are used to measure outgoing quality levels.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGSTotal Supply Voltage +VS to –VS . . . . . . . . . . . . . . . . . . 36V
Maximum Input Voltage (Figure 6) . . . . . . . . . . . . . . . . . 36 V
Maximum Output Current (Open Collector Output) . .50 mA
Amplifier Short Circuit to Ground . . . . . . . . . . . . . Indefinite
Storage Temperature Range:Cerdip . . . . . . –65°C to +150°C
Storage Temperature Range:PLCC . . . . . . –65°C to +150°C
DEFINITIONS OF SPECIFICATIONSGAIN ERROR—The gain of a voltage-to-frequency converter is
that scale factor setting that provides the nominal conversion
relationship, e.g., 1 MHz full scale. The “gain error” is the dif-
ference in slope between the actual and ideal transfer functions
for the V-F converter.
LINEARITY ERROR—The “linearity error” of a V-F is the
deviation of the actual transfer function from a straight line
passing through the endpoints of the transfer function.
GAIN TEMPERATURE COEFFICIENT—The gain tempera-
ture coefficient is the rate of change in full-scale frequency as a
AD652
ORDERING GUIDENOTESFor details on grade and package offerings screened in accordance with MIL-
STD-883, refer to the Analog Devices Military Products Databook or current
AD652/883 data sheet.P = Plastic Leaded Chip Carrier; Q = Cerdip.
PIN CONFIGURATIONS
THEORY OF OPERATIONA synchronous VFC is similar to other voltage-to-frequency
converters in that an integrator is used to perform a charge-
balance of the input signal with an internal reference current.
However, rather than using a one-shot as the primary timing
element which requires a high quality and low drift capacitor,
a synchronous voltage-to-frequency converter (SVFC) uses an
external clock; this allows the designer to determine the system
stability and drift based upon the external clock selected. A crys-
tal oscillator may also be used if desired.
The SVFC architecture provides other system advantages besides
low drift. If the output frequency is measured by counting
pulses gated to a signal which is derived from the clock, the
clock stability is unimportant and the device simply performs as a
voltage controlled frequency divider, producing a high resolution
A/D. If a large number of inputs must be monitored simulta-
neously in a system, the controlled timing relationship between
the frequency output pulses and the user supplied clock greatly
simplifies this signal acquisition. Also, if the clock signal is pro-
vided by a VFC, then the output frequency of the SVFC will be
proportional to the product of the two input voltages.
Figure 1a.Cerdip Pin Configuration
The pinouts of the AD652 SVFC are shown in Figure 1. A
block diagram of the device configured as a SVFC, along with
various system waveforms, is shown in Figure 2.
Figure 1b.PLCC Pin Configuration
Figure 2 shows the typical up-and-down ramp integrator output
of a charge-balance VFC. After the integrator output has crossed
the comparator threshold and the output of the AND gate has
gone high, nothing happens until a negative edge of the clock
comes along to transfer the information to the output of the
D-FLOP. At this point, the clock level is low, so the latch does
not change state. When the clock returns high, the latch output
goes high and drives the switch to reset the integrator. At the
same time the latch drives the AND gate to a low output state.
On the very next negative edge of the clock the low output state
of the AND gate is transferred to the output of the D-FLOP
and then when the clock returns high, the latch output goes low
and drives the switch back into the Integrate Mode. At the same
time the latch drives the AND gate to a mode where it will truth-
fully relay the information presented to it by the comparator.
Since the reset pulses applied to the integrator are exactly one
clock period long, the only place where drift can occur is in a
there are no problems with dielectric absorption causing the
duration of a reset pulse to be influenced by the length of time
since the last reset.
Figure 2. AD652 Block Diagram and System Waveforms
Referring to Figure 2, it can be seen that the period between
output pulses is constrained to be an exact multiple of the clock
period. Consider an input current of exactly one quarter of the
value of the reference current. In order to achieve a charge bal-
ance, the output frequency will equal the clock frequency divided
by four; one clock period for reset and three clock periods of inte-
grate. This is shown in Figure 3. If the input current is increased by
a very small amount, the output frequency should also increase
by a very small amount. Initially, however, no output change is
Figure 3. Integrator Output for lIN = 250 µA
observed for a very small increase in the input current. The out-
put frequency continues to run at one quarter of the clock,
delivering an average of 250 µA to the summing junction. Since
the input current is slightly larger than this, charge accumulates
finally, a whole cycle is lost. When the cycle is lost, the Integrate
Phase lasts for two periods of the clock instead of the usual three
periods. Thus, among a long string of divide-by-fours an occasional
divide-by-three occurs; the average of the output frequency is
very close to one quarter of the clock, but the instantaneous fre-
quency can be very different.
Because of this, it is very difficult to observe the waveform on an
oscilloscope. During all of this time, the signal at the output of
the integrator is a sawtooth wave with an envelope which is also
a sawtooth. This is shown in Figure 4.
Figure 4. Integrator Output for IIN Slightly Greater
than 250 µA
Another way to view this is that the output is a frequency of
approximately one quarter of the clock that has been phase
modulated. A constant frequency can be thought of as accumu-
lating phase linearly with time at a rate equal to 2 πf radians per
second. Hence, the average output frequency which is slightly in
excess of a quarter of the clock will require phase accumulation
at a certain rate. However, since the SVFC is running at exactly
one quarter of the clock, it will not accumulate enough phase
(see Figure 5). When the difference between the required phase
(average frequency) and the actual phase equals 2 π, a step in
phase is taken where the deficit is made up instantaneously. The
output frequency is then a steady carrier which has been phase
modulated by a sawtooth signal (see Figure 5). The period of
the sawtooth phase modulation is the time required to accumulate
a 2 π difference in phase between the required average frequency
and one quarter of the clock frequency. The amplitude of the
sawtooth phase modulation is 2 π.
