AD650BD ,Voltage-to-Frequency and Frequency-to-Voltage ConverterSPECIFICATIONSS AD650J/AD650A AD650K/AD650B AD650SModel Min Typ Max Min Typ ..
AD650JN ,Voltage-to-Frequency and Frequency-to-Voltage ConverterSPECIFICATIONSS AD650J/AD650A AD650K/AD650B AD650SModel Min Typ Max Min Typ ..
AD650JP ,Voltage-to-Frequency and Frequency-to-Voltage Converterapplications requiring high resolution monotonic A/Danalog-to-digital converter circuit. Higher ful ..
AD650KN ,Voltage-to-Frequency and Frequency-to-Voltage Converterspecifications.REV. CInformation furnished by Analog Devices is believed to be accurate andreliable ..
AD650SD ,Voltage-to-Frequency and Frequency-to-Voltage ConverterFEATURESV/F Conversion to 1 MHzReliable Monolithic ConstructionVery Low Nonlinearity0.002% typ at 1 ..
AD650SD ,Voltage-to-Frequency and Frequency-to-Voltage ConverterSpecifications shown in boldface are tested on all production units at final electrical test. Resul ..
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ADC0800PCD ,ADC0800 8-Bit A/D ConverterADC08008-BitA/DConverterFebruary1995ADC08008-BitA/DConverterGeneralDescription
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AD650AD-AD650BD-AD650JN-AD650JP-AD650KN-AD650SD
Voltage-to-Frequency and Frequency-to-Voltage Converter
PIN CONFIGURATIONREV.C
Voltage-to-Frequency and
Frequency-to-Voltage Converter
FEATURES
V/F Conversion to 1 MHz
Reliable Monolithic Construction
Very Low Nonlinearity
0.002% typ at 10 kHz
0.005% typ at 100 kHz
0.07% typ at 1 MHz
Input Offset Trimmable to Zero
CMOS or TTL Compatible
Unipolar, Bipolar, or Differential V/F
V/F or F/V Conversion
Available in Surface Mount
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTIONThe AD650 V/F/V (voltage-to-frequency or frequency-to-voltage
converter) provides a combination of high frequency operation
and low nonlinearity previously unavailable in monolithic form.
The inherent monotonicity of the V/F transfer function makes
the AD650 useful as a high-resolution analog-to-digital converter.
A flexible input configuration allows a wide variety of input volt-
age and current formats to be used, and an open-collector output
with separate digital ground allows simple interfacing to either
standard logic families or opto-couplers.
The linearity error of the AD650 is typically 20 ppm (0.002%
of full scale) and 50 ppm (0.005%) maximum at 10 kHz full
scale. This corresponds to approximately 14-bit linearity in an
analog-to-digital converter circuit. Higher full-scale frequencies
or longer count intervals can be used for higher resolution con-
versions. The AD650 has a useful dynamic range of six decades
allowing extremely high resolution measurements. Even at 1 MHz
full scale, linearity is guaranteed less than 1000 ppm (0.1%) on
the AD650KN, BD, and SD grades.
In addition to analog-to-digital conversion, the AD650 can be used
in isolated analog signal transmission applications, phased locked-
loop circuits, and precision stepper motor speed controllers. In
the F/V mode, the AD650 can be used in precision tachometer
and FM demodulator circuits.
The input signal range and full-scale output frequency are user-
programmable with two external capacitors and one resistor.
Input offset voltage can be trimmed to zero with an external
potentiometer.
The AD650JN and AD650KN are offered in a plastic 14-lead
DIP package. The AD650JP is available in a 20-lead plastic
leaded chip carrier (PLCC). Both plastic packaged versions of the
AD650 are specified for the commercial (0°C to +70°C) tempera-
ture range. For industrial temperature range (–25°C to +85°C)
applications, the AD650AD and AD650BD are offered in a
ceramic package. The AD650SD is specified for the full –55°C
to +125°C extended temperature range.
PRODUCT HIGHLIGHTSIn addition to very high linearity, the AD650 can operate at
full-scale output frequency up to 1 MHz. The combination of
these two features makes the AD650 an inexpensive solution
for applications requiring high resolution monotonic A/D
conversion.The AD650 has a very versatile architecture that can be con-
figured to accommodate bipolar, unipolar, or differential
input voltages, or unipolar input currents.TTL or CMOS compatibility is achieved using an open
collector frequency output. The pull-up resistor can be
connected to voltages up to +30 V, or +15 V or +5 V for
conventional CMOS or TTL logic levels.The same components used for V/F conversion can also be
used for F/V conversion by adding a simple logic biasing net-
work and reconfiguring the AD650.The AD650 provides separate analog and digital grounds.
This feature allows prevention of ground loops in real-world
applications.The AD650 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD650/883B data sheet for detailed
specifications.
DYNAMIC RESPONSE
COMPARATOR (F/V Conversion)
OPEN COLLECTOR OUTPUT (V/F Conversion)
NOTES
1Nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a fraction of full scale.Full-scale calibration error adjustable to zero.
3Measured at full-scale output frequency of 100 kHz.Refer to F/V conversion section of the text.Referred to digital ground.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those test are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested on all production units.
AD650–SPECIFICATIONS(@ +25�C, with VS = �15 V, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGSTotal SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Storage Temperature . . . . . . . . . . . . . . . . . . .–55°C to +150°C
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .±10 V
Maximum Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .±VS
Open Collector Output Voltage Above Digital GND . . . . .36 V
Open Collector Output Current . . . . . . . . . . . . . . . . . .50 mA
Amplifier Short Circuit to Ground . . . . . . . . . . . . . .Indefinite
Comparator Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . .±VS
PIN CONFIGURATION
ORDERING GUIDE
AD650
CIRCUIT OPERATION
UNIPOLAR CONFIGURATIONThe AD650 is a charge balance voltage-to-frequency converter. In
the connection diagram shown in Figure 1, or the block diagram
of Figure 2a, the input signal is converted into an equivalent cur-
rent by the input resistance RIN. This current is exactly balanced
by an internal feedback current delivered in short, timed bursts
from the switched 1 mA internal current source. These bursts of
current may be thought of as precisely defined packets of charge.
The required number of charge packets, each producing one
pulse of the output transistor, depends upon the amplitude of
the input signal. Since the number of charge packets delivered
per unit time is dependent on the input signal amplitude, a linear
voltage-to-frequency transformation will be accomplished. The
frequency output is furnished via an open collector transistor.
A more rigorous analysis demonstrates how the charge balance
voltage-to-frequency conversion takes place.
A block diagram of the device arranged as a V-to-F converter is
shown in Figure 2a. The unit is comprised of an input integra-
tor, a current source and steering switch, a comparator and a
one-shot. When the output of the one-shot is low, the current
steering switch S1 diverts all the current to the output of the op
amp; this is called the Integration Period. When the one-shot
has been triggered and its output is high, the switch S1 diverts
all the current to the summing junction of the op amp; this is
called the Reset Period. The two different states are shown in
Figure 2 along with the various branch currents. It should be
noted that the output current from the op amp is the same for
either state, thus minimizing transients.
Figure 1.Connection Diagram for V/F Conversion,
Positive Input Voltage
Figure 2b.Reset Mode Figure 2c.Integrate Mode
Figure 2d.Voltage Across CINT
The positive input voltage develops a current (IIN = VIN/RIN)
which charges the integrator capacitor CINT. As charge builds up
on CINT, the output voltage of the integrator ramps downward
towards ground. When the integrator output voltage (Pin 1)
crosses the comparator threshold (–0.6 volt) the comparator
triggers the one shot, whose time period, tOS is determined by
the one shot capacitor COS.
Specifically, the one shot time period is:
(1)The Reset Period is initiated as soon as the integrator output
voltage crosses the comparator threshold, and the integrator
ramps upward by an amount:
After the Reset Period has ended, the device starts another Inte-
gration Period, as shown in Figure 2, and starts ramping downward
again. The amount of time required to reach the comparator
threshold is given as:
(3)
The output frequency is now given as:
Note that CINT, the integration capacitor has no effect on the
transfer relation, but merely determines the amplitude of the
sawtooth signal out of the integrator.
One Shot TimingA key part of the preceding analysis is the one shot time period
at analog ground is opened allowing that voltage to change. An
internal 0.5 mA current source connected to Pin 6 then draws
its current out of COS, causing the voltage at Pin 6 to decrease
linearly. At approximately –3.4 V, the one shot resets itself,
thereby ending the timed period and starting the V/F conversion
cycle over again. The total one shot time period can be written
mathematically as:
(5)
substituting actual values quoted above,
(6)
This simplifies into the timed period equation given above.
COMPONENT SELECTIONOnly four component values must be selected by the user. These
are input resistance RIN, timing capacitor COS, logic resistor R2,
and integration capacitor CINT. The first two determine the
input voltage and full-scale frequency, while the last two are
determined by other circuit considerations.
Of the four components to be selected, R2 is the easiest to
define. As a pull-up resistor, it should be chosen to limit the
current through the output transistor to 8 mA if a TTL maxi-
mum VOL of 0.4 V is desired. For example, if a 5 V logic supply
is used, R2 should be no smaller than 5 V/8 mA or 625 Ω. A
larger value can be used if desired.
RIN and COS are the only two parameters available to set the
full- scale frequency to accommodate the given signal range.
The “swing” variable that is affected by the choice of RIN and
COS is nonlinearity. The selection guide of Figure 3 shows this
quite graphically. In general, larger values of COS and lower
full-scale input currents (higher values of RIN) provide better
linearity. In Figure 3, the implications of four different choices
of RIN are shown. Although the selection guide is set up for a
unipolar configuration with a zero to 10 V input signal range,
the results can be extended to other configurations and input
signal ranges. For a full scale frequency of 100 kHz (corre-
sponding to 10 V input), you can see that among the available
choices, RIN = 20 k and COS = 620 pF gives the lowest nonlin-
earity, 0.0038%. Also, if you wish to use the highest frequency
that will give the 20 ppm minimum nonlinearity, it is approxi-
mately 33 kHz (40.2 kΩ and 1000 pF).
For input signal spans other than 10 V, the input resistance
must be scaled proportionately. For example, if 100 kΩ is called
out for a 0 V–10 V span, 10k would be used with a 0 V–1 V
span, or 200 kΩ with a ±10 V bipolar connection.
The last component to be selected is the integration capacitor
CINT. In almost all cases, the best value for CINT can be calcu-
lated using the equation:
Figure 3a.Full-Scale Frequency vs. COS
Figure 3b.Typical Nonlinearity vs. COS
can be rejected. If the output frequency is measured by counting
pulses during a constant gate period, the integration provides
infinite normal-mode rejection for frequencies corresponding to
the gate period and its harmonics. However, if the integrator
stage becomes saturated by an excessively large noise pulse, the
continuous integration of the signal will be interrupted, allowing
the noise to appear at the output. If the approximate amount of
noise that will appear on CINT is known (VNOISE), the value of
CINT can be checked using the following inequality:
For example, consider an application calling for a maximum
frequency of 75 kHz, a 0 volt–1 volt signal range, and supply
voltages of only ±9 volts. The component selection guide of Fig-
ure 3 is used to select 2.0 kΩ for RIN and 1000 pF for COS. This
results in a one shot time period of approximately 7 µs. Sub-
stituting 75 kHz into equation 7 yields a value of 1300 pF for
CINT. When the input signal is near zero, 1 mA flows through the
integration capacitor to the switched current sink during the reset
phase, causing the voltage across CINT to increase by approximately
5.5 volts. Since the integrator output stage requires approximately
3 volts head room for proper operation, only 0.5 volt margin
remains for integrating extraneous noise on the signal line. A
AD650
BIPOLAR V/FFigure 4 shows how the internal bipolar current sink is used to
provide a half-scale offset for a ±5 V signal range, while provid-
ing a 100 kHz maximum output frequency. The nominally 0.5 mA
(±10%) offset current sink is enabled when a 1.24 kΩ resistor is
connected between Pins 4 and 5. Thus, with the grounded 10 kΩ
nominal resistance shown, a –5 V offset is developed at Pin 2.
Since Pin 3 must also be at –5 V, the current through RIN is
10 V/40 kΩ = +0.25 mA at VIN = +5 V, and 0 mA at
VIN = –5 V.
Components are selected using the same guidelines outlined for
the unipolar configuration with one alteration. The voltage
across the total signal range must be equated to the maximum
Figure 4.Connections for ±5 V Bipolar V/F with 0 to
100 kHz TTL Output
input voltage in the unipolar configuration. In other words, the
value of the input resistor RIN is determined by the input voltage
span, not the maximum input voltage. A diode from Pin 1 to
ground is also recommended. This is further discussed in the
Other Circuit Conditions section.
As in the unipolar circuit, RIN and COS must have low tempera-
ture coefficients to minimize the overall gain drift. The 1.24 kΩ
resistor used to activate the 0.5 mA offset current should also
have a low temperature coefficient. The bipolar offset current
has a temperature coefficient of approximately –200 ppm/°C.
UNIPOLAR V/F, NEGATIVE INPUT VOLTAGEFigure 5 shows the connection diagram for V/F conversion of
negative input voltages. In this configuration full-scale output
frequency occurs at negative full-scale input, and zero output
frequency corresponds with zero input voltage.
A very high impedance signal source may be used since it only
drives the noninverting integrator input. Typical input imped-
ance at this terminal is 1 GΩ or higher. For V/F conversion of
positive input signals using the connection diagram of Figure 1,
the signal generator must be able to source the integration cur-
rent to drive the AD650. For the negative V/F conversion circuit
of Figure 5, the integration current is drawn from ground
through R1 and R3, and the active input is high impedance.
Circuit operation for negative input voltages is very similar to
Figure 5.Connection Diagram for V/F Conversion,
Negative Input Voltage
F/V CONVERSIONThe AD650 also makes a very linear frequency-to-voltage
converter. Figure 6 shows the connection diagram for F/V con-
version with TTL input logic levels. Each time the input signal
crosses the comparator threshold going negative, the one shot is
activated and switches 1 mA into the integrator input for a
measured time period (determined by COS). As the frequency
increases, the amount of charge injected into the integration
capacitor increase proportionately. The voltage across the inte-
gration capacitor is stabilized when the leakage current through
R1 and R3 equals the average current being switched into the
integrator. The net result of these two effects is an average output
voltage which is proportional to the input frequency. Optimum
performance can be obtained by selecting components using the
same guidelines and equations listed in the V/F Conversion section.
The reader is referred to Analog Devices' Application Note
AN-279 where a more complete description of this application
can be found.
Figure 6. Connection Diagram for F/V Conversion
HIGH FREQUENCY OPERATIONProper RF techniques must be observed when operating the
AD650 at or near its maximum frequency of 1 MHz. Lead
lengths must be kept as short as possible, especially on the one
shot and integration capacitors, and at the integrator summing
junction. In addition, at maximum output frequencies above
