AD641AN-AD641AP Fast Delivery |IC PHOENIX CO.,LIMITED

AD641AP ,250 MHz Demodulating Logarithmic AmplifierSpecifications subject to change without notice.–2– REV. CAD641ORDERING GUIDEABSOLUTE MAXIMUM RATIN ..
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AD641AN-AD641AP
250 MHz Demodulating Logarithmic Amplifier
REV. C
250 MHz Demodulating
Logarithmic Amplifier
FEATURES
Logarithmic Amplifier Performance
Usable to 250MHzdB Dynamic Range
62.0dB Log Conformance
37.5mV/dB Voltage Output
Stable Slope and Intercepts
2.0nV/√Hz Input Noise VoltagemV Input Offset Voltage
Low PowerV Supply OperationmA (+VS), 35mA (–VS) Quiescent Current
Onboard Resistors
Onboard 103 Attenuator
Dual Polarity Current Outputs
Direct Coupled Differential Signal Path
APPLICATIONS
IF/RF Signal Processing
Received Signal Strength Indicator (RSSI)
High Speed Signal Compression
High Speed Spectrum Analyzer
ECM/Radar
PIN CONFIGURATIONS
20-Lead Plastic DIP (N)
20-Lead Cerdip (Q)
ATN COMCKT COM
–INPUT
ATN LO
ATN COM
ATN IN
BL1
–VS
ITC
–OUTPUT
BL2
ATN OUT
+INPUT
RG1
RG0
RG2
LOG OUT
LOG COM
+VS
+OUTPUT
20-Lead PLCC (P)ATN COMCKT COM
ATN COMATN LO–INPUT+INPUTATN OUT
BL2
SIG –OUTSIG +OUT
LOG COM
ATN IN
BL1
–VS
ITC
RG1
RG0
RG2
LOG OUT
PRODUCT DESCRIPTION
The AD641 is a 250 MHz, demodulating logarithmic amplifier
with an accuracy of –2.0 dB and 44 dB dynamic range. The
AD641 uses a successive detection architecture to provide an
output current that is logarithmically proportional to its input
voltage. The output current can be converted to a voltage using
one of several on-chip resistors to select the slope. A single
AD641 provides up to 44 dB of dynamic range at speeds up to
250 MHz, and two cascaded AD641s together can providedB of dynamic range at speeds up to 250 MHz. The AD641
is fully stable and well characterized over either the industrial or
military temperature ranges.
The AD641 is not a logarithmic building block, but rather a
complete logarithmic solution for compressing and measuring
wide dynamic range signals. The AD641 is comprised of five
stages and each stage has a full wave rectifier, whose current
depends on the absolute value of its input voltage. The output
of these stages are summed together to provide the demodulated
output current scaled at 1 mA per decade (50 mA/dB).
Without utilizing the 10· input attenuator, log conformance of
2.0 dB is maintained over the input range –44 dBm to 0 dBm.
The attenuator offers the most flexibility without significantly
impacting performance.
The 250 MHz bandwidth and temperature stability make this
product ideal for high speed signal power measurement in RF/
IF systems. ECM/Radar and Communication applications are
routinely in the 100MHz–180 MHz range for power measure-
ment. The bandwidth and accuracy, as well as dynamic range,
make this part ideal for high speed, wide dynamic range signals.
The AD641 is offered in industrial (–40°C to +85°C) and mili-
tary (–55°C to +125°C) package temperature ranges. Industrial
versions are available in plastic DIP and PLCC; MIL versions
are packaged in cerdip.
AD641–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
LOG AMPLIFIER PERFORMANCE
LOG CONFORMANCE
INPUT CHARACTERISTICS
APPLICATION RESISTORS
POWER SUPPLY
NOTES
1Logarithms to base 10 are used throughout. The response is independent of the sign of VIN.
(VS = 65 V; TA = +258C, unless otherwise noted)
ORDERING GUIDE
THERMAL CHARACTERISTICS
20-Lead Plastic DIP Package (N)
20-Lead Cerdip Package (Q)
ABSOLUTE MAXIMUM RATINGS*
Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7.5 V
Input Voltage (Pin 1 or Pin 20 to COM) . . . –3 V to +300 mV
Attenuator Input Voltage (Pin 5 to Pin 3/4) . . . . . . . . . . . –4 V
Storage Temperature Range, Q . . . . . . . . . . –65°C to +150°C
Storage Temperature Range, N, P . . . . . . . . –65°C to +125°C
Ambient Temperature Range, Rated Performance
Industrial, AD641A . . . . . . . . . . . . . . . . . . –40°C to +85°C
Military, AD641S . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may adversely affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD641 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD641
–Typical DC Performance Characteristics
TEMPERATURE – 8C
SLOPE CURRENT – mA
Figure 1.Slope Current, IY, vs.
Temperature
POWER SUPPLY VOLTAGES – 6 Volts
INTERCEPT VOLTAGE – mV
0.985
Figure 4.Intercept Voltage, VX, vs.
Supply Voltages
Figure 7.DC Logarithmic Transfer
Function and Error Curve for Single
AD641
TEMPERATURE – 8C
INTERCEPT – mV
0.85
Figure 2.Intercept Voltage, VX, vs.
Temperature
TEMPERATURE – 8C
INTERCEPT – mV
Figure 5.Intercept Voltage (Using
Attenuator) vs. Temperature
TEMPERATURE – 8C
ABSOLUTE ERROR – dB
Figure 8.Absolute Error vs. Tempera-
ture, VIN = –1 mV to –100 mV
Figure 3.Slope Current, IY, vs. Supply
Voltages
TEMPERATURE – 8C
DEVIATION OF INPUT OFFSET VOLTAGE – mV
+0.4
+0.3
+0.2
+0.1
–0.3
Figure 6.Input Offset Voltage Devia-
tion vs. Temperature
TEMPERATURE – 8C
ABSOLUTE ERROR – dB
Figure 9.Absolute Error vs. Tempera-
ture, Using Attenuator. VIN = –10 mV
to –1 V, Pin 8 Grounded to Disable ITC
Bias
INPUT LEVEL – dBm
OUTPUT CURRENT – mA
50MHz
150MHz
190MHz
210MHz
250MHz
Figure 10.AC Response at 50 MHz, 150 MHz, 190 MHz,
210MHz at 250 MHz, vs. dBm Input (Sinusoidal Input)
INPUT FREQUENCY – MHz
INTERCEPT LEVEL – dBm
82.5
Figure 11.Intercept Level (dBm) vs. Frequency (Cascaded
AD641s—Sinusoidal Input)
Figure 12.Baseband Pulse Response of Single AD641,
Inputs of 1 mV, 10 mV and 100 mV
ERROR IN – dB
INPUT LEVEL – dBm
OUTPUT – mA
–52–36–32–28–24–20–16–12–80
Figure 13.Logarithmic Response and Linearity at
200MHz, TA for TA = –55°C, +25°C, +125°C
INPUT FREQUENCY – MHz
SLOPE CURRENT – mA
Figure 14.Slope Current, IY, vs. Input Frequency
Figure 15.Baseband Pulse Response of Cascaded AD641s
at Inputs of 0.2 mV, 2 mV, 20 mV and 200 mV
AD641
ATN LO
ATN COM
SIG +IN
SIG –IN
COMRG1RG0RG2
+VS
LOG OUTLOG COM
SIG +OUT
SIG –OUT
BL2
ATN OUT
CIRCUIT DESCRIPTION
The AD641 uses five cascaded limiting amplifiers to approxi-
mate a logarithmic response to an input signal of wide dynamic
range and wide bandwidth. This type of logarithmic amplifier
has traditionally been assembled from several small scale ICs
and numerous external components. The performance of these
semidiscrete circuits is often unsatisfactory. In particular, the
logarithmic slope and intercept (see FUNDAMENTALS OF
LOGARITHMIC CONVERSION) are usually not very stable
in the presence of supply and temperature variations even after
laborious and expensive individual calibration. The AD641 em-
ploys high precision analog circuit techniques to ensure stability
of scaling over wide variations in supply voltage and tempera-
ture. Laser trimming, using ac stimuli and operating conditions
similar to those encountered in practice, provides fully cali-
brated logarithmic conversion.
Each of the amplifier/limiter stages in the AD641 has a small
signal voltage gain of 10 dB (·3.162) and a –3 dB bandwidth of
350 MHz. Fully differential direct coupling is used throughout.
This eliminates the many interstage coupling capacitors usually
required in ac applications, and simplifies low frequency signal
processing, for example, in audio and sonar systems. The AD641
is intended for use in demodulating applications. Each stage
incorporates a detector (a full-wave transconductance rectifier)
whose output current depends on the absolute value of its input
voltage.
Figure 16 is a simplified schematic of one stage of the AD641.
All transistors in the basic cell operate at near zero collector to
base voltage and low bias currents, resulting in low levels of
thermally induced distortion. These arise when power shifts
from one set of transistors to another during large input signals.
Rapid recovery is essential when a small signal immediately
follows a large one. This low power operation also contributes
significantly to the excellent long term calibration stability of the
AD641.
The complete AD641, shown in Figure 17, includes two bias
regulators. One determines the small signal gain of the ampli-
fier stages; the other determines the logarithmic slope. These
bias regulators maintain a high degree of stability in the re-
sulting function by compensating for potentially large uncer-
tainties in transistor parameters, temperature and supply
voltages. A third biasing block is used to accurately control
the logarithmic intercept.
COMMON
SIG
SIG
OUT
LOG OUTLOG COM
–VS
1.09mA
PTAT
1.09mA
PTAT
565mA565mA2.18mA
PTAT
Figure 16.Simplified Schematic of a Single AD641 Stage
By summing the signals at the output of the detectors, a good
approximation to a logarithmic transfer function can be achieved.
The lower the stage gain, the more accurate the approximation,
but more stages are then needed to cover a given dynamic range.
The choice of 10 dB results in a theoretical periodic deviation or
ripple in the transfer function of –0.15 dB from the ideal re-
sponse when the input is either a dc voltage or a square wave.
The slope of the transfer function is unaffected by the input
waveform; however, the intercept and ripple are waveform de-
pendent (see EFFECT OF WAVEFORM ON INTERCEPT).
The input will usually be an amplitude modulated sinusoidal
carrier. In these circumstances the output is a fluctuating cur-
rent at twice the carrier frequency (because of the full wave
detection) whose average value is extracted by an external low
pass filter, which recovers a logarithmic measure of the base-
band signal.
Circuit Operation
With reference to Figure 16, the transconductance pair Q7, Q8
and load resistors R3 and R4 form a limiting amplifier having a
small signal gain of 10 dB, set by the tail current of nominally
2.18 mA at 27°C. This current is basically proportional to abso-
lute temperature (PTAT) but includes additional current to
compensate for finite beta and junction resistance. The limiting
output voltage is –180 mV at +27°C and is PTAT. Emitter
followers Q1 and Q2 raise the input resistance of the stage,
provide level shifting to introduce collector bias for the gain
stage and detectors, reduce offset drift by forming a thermally
balanced quad with Q7 and Q8 and generate the detector bias-
ing across resistors R1 and R2.
Transistors Q3 through Q6 form the full wave detector, whose
output is buffered by the cascodes Q9 and Q10. For zero input
Q3 and Q5 conduct only a small amount (a total of about 32mA)
of the 565mA tail currents supplied to pairs Q3–Q4 and Q5–Q6.
This “pedestal” current flows in output cascode Q9 to the LOG
OUT node (Pin 14). When driven to the peak output of the
preceding stage, Q3 or Q5 (depending on signal polarity) con-
ducts most of the tail current, and the output rises to 532mA.
The LOG OUT current has thus changed by 500mA as the
input has changed from zero to its maximum value. Since the
detectors are spaced at 10 dB intervals, the output increases bymA/dB, or 1 mA per decade. This scaling parameter is trimmed
to absolute accuracy using a 2 kHz square wave. At frequencies
near the system bandwidth, the slope is reduced due to the
reduced output of the limiter stages, but it is still relatively in-
sensitive to temperature variations so that a simple external
slope adjustment can restore scaling accuracy.
The intercept position bias generator (Figure 17) removes the
pedestal current from the summed detector outputs. It is ad-
justed during manufacture such that the output (flowing into
Pin 14) is 1 mA when a 2 kHz square-wave input of exactly10mV is applied to the AD641. This places the dc intercept at
precisely 1 mV. The LOG COM output (Pin 13) is the comple-
ment of LOG OUT. It also has a 1 mV intercept, but with an
inverted slope of –1 mA/decade. Because its pedestal is very
large (equivalent to about 100 dB), its intercept voltage is not
guaranteed. The intercept positioning currents include a special
internal temperature compensation (ITC) term which can be
disabled by connecting Pin 8 to ground.
The logarithmic function of the AD641 is absolutely calibrated
to within –0.3 dB (or –15mA) for 2 kHz square-wave inputs of1mV to –100mV, and to within –1 dB between –750mV and200mV. Figure 18 is a typical plot of the dc transfer function,
INPUT VOLTAGE – mV
OUTPUT CURRENT – mA
ABSOLUTE ERROR – dB
Figure 18.Logarithmic Output and Absolute Error vs. DC
or Square Wave Input at TA = –55°C, +25°C, and +125°C,
Input Direct to Pins 1 and 20
INPUT VOLTAGE – mV
OUTPUT CURRENT – mA
ABSOLUTE ERROR – dB
Figure 19.Logarithmic Output and Absolute Error vs. DC
or Square Wave Input at TA = –55°C, +25°C, +85°C and
+125°C. Input via On-Chip Attenuator
showing the outputs at temperatures of –55°C, +25°C and
+125°C. While the slope and intercept are seen to be little af-
fected by temperature, there is a lateral shift in the end points of
the “linear” region of the transfer function, which reduces the
effective dynamic range.
The on chip attenuator can be used to handle input levels 20dB
higher, that is, from –7.5mV to –2V for dc or square wave
inputs. It is specially designed to have a positive temperature
coefficient and is trimmed to position the intercept at 10mV dc
(or –24dBm for a sinusoidal input) over the full temperature
range. When using the attenuator the internal bias compensa-
tion should be disabled by grounding Pin 8. Figure 19 shows
the output at –55°C, +25°C, +85°C and +125°C for a single,
AD641 with the attenuator in use; the curves overlap almost
perfectly, and the lateral shift in the transfer function does not
occur. Therefore, the full dynamic range is available at all
temperatures.
The output of the final limiter is available in differential form at
Pins 10 and 11. The output impedance is 75W to ground from
either pin. For most input levels, this output will appear to have
roughly a square waveform. The signal path may be extended
using these outputs (see OPERATION OF CASCADED
AD641s). The logarithmic outputs from two or more AD641s
can be directly summed with full accuracy.
A pair of 1kW applications resistors, RG1 and RG2 (Figure 17)
are accessed via Pins 15, 16 and 17. These can be used to con-
vert an output current to a voltage, with a slope of 1V/decade
(using one resistor), 2V/decade (both resistors in series) or
0.5V/decade (both in parallel). Using all the resistors from two
AD641s (for example, in a cascaded configuration) ten slope
options from 0.25V to 4V/decade are available.
AD641
FUNDAMENTALS OF LOGARITHMIC CONVERSION
The conversion of a signal to its equivalent logarithmic value
involves a nonlinear operation, the consequences of which can be
very confusing if not fully understood. It is important to realize
from the outset that many of the familiar concepts of linear
circuits are of little relevance in this context. For example, the
incremental gain of an ideal logarithmic converter approaches
infinity as the input approaches zero. Further, an offset at the
output of a linear amplifier is simply equivalent to an offset at
the input, while in a logarithmic converter it is equivalent to a
change of amplitude at the input—a very different relationship.
We assume a dc signal in the following discussion to simplify the
concepts; ac behavior and the effect of input waveform on cali-
bration are discussed later. A logarithmic converter having a
voltage input VIN and output VOUT must satisfy a transfer func-
tion of the form
VOUT = VY LOG (VIN/VX)Equation (1)
where VY and VX are fixed voltages which determine the scaling
of the converter. The input is divided by a voltage because the
argument of a logarithm has to be a simple ratio. The logarithm
must be multiplied by a voltage to develop a voltage output.
These operations are not, of course, carried out by explicit com-
putational elements, but are inherent in the behavior of the
converter. For stable operation, VX and VY must be based on
sound design criteria and rendered stable over wide temperature
and supply voltage extremes. This aspect of RF logarithmic
amplifier design has traditionally received little attention.
When VIN = VX, the logarithm is zero. VX is, therefore, called
the Intercept Voltage, because a graph of VOUT versus LOG
(VIN)—ideally a straight line—crosses the horizontal axis at this
point (see Figure 20). For the AD641, VX is calibrated to ex-
actly 1mV. The slope of the line is directly proportional to VY.
Base 10 logarithms are used in this context to simplify the rela-
tionship to decibel values. For VIN = 10VX, the logarithm has a
value of 1, so the output voltage is VY. At VIN = 100VX, the
output is 2VY, and so on. VY can therefore be viewed either as
the Slope Voltage or as the Volts per Decade Factor.
The AD641 conforms to Equation (1) except that its two out-
puts are in the form of currents, rather than voltages:
IOUT = IY LOG (VIN/VX)Equation (2)
2VY
IY, the Slope Current, is 1mA. The current output can readily
be converted to a voltage with a slope of 1V/decade, for ex-
ample, using one of the 1kW resistors provided for this purpose,
in conjunction with an op amp, as shown in Figure 21.
1V PER DECADE
FOR R2 = 1kV
100mV PER dB
FOR R2 = 2kV
Figure 21.Using an External Op Amp to Convert the
AD641 Output Current to a Buffered Voltage Output
Intercept Stabilization
Internally, the intercept voltage is a fraction of the thermal volt-
age kT/q, that is, VX = VXOT/TO, where VXO is the value of VX
at a reference temperature TO. So the uncorrected transfer
function has the form:
IOUT = IY LOG (VIN TO/VXOT)Equation (3)
Now, if the amplitude of the signal input VIN could somehow be
rendered PTAT, the intercept would be stable with tempera-
ture, since the temperature dependence in both the numerator
and denominator of the logarithmic argument would cancel.
This is what is actually achieved by interposing the on-chip
attenuator, which has the necessary temperature dependence to
cause the input to the first stage to vary in proportion to abso-
lute temperature. The end limits of the dynamic range are now
totally independent of temperature. Consequently, this is the pre-
ferred method of intercept stabilization for applications where
the input signal is sufficiently large.
When the attenuator is not used, the PTAT variation in VX will
result in the intercept being temperature dependent. Near 300K
(+27°C) it will vary by 20 LOG (301/300) dB/°C, about 0.03dB/
°C. Unless corrected, the whole output function would drift up
or down by this amount with changes in temperature. In the
AD641 a temperature compensating current IYLOG(T/TO) is
added to the output. This effectively maintains a constant inter-
cept VXO. This correction is active in the default state (Pin 8
open circuited). When using the attenuator, Pin 8 should be
grounded, which disables the compensation current. The drift
term needs to be compensated only once; when the outputs of
two AD641s are summed, Pin 8 should be grounded on at least
one of the two devices (both if the attenuator is used).
Conversion Range
Practical logarithmic converters have an upper and lower limit
on the input, beyond which errors increase rapidly. The upper
limit occurs when the first stage in the chain is driven into limit-
ing. Above this, no further increase in the output can occur and
the transfer function flattens off. The lower limit arises because

Partno	Mfg	Dc	Qty	Available	Descript
AD641AN	AD	N/a	3	avai	250 MHz Demodulating Logarithmic Amplifier
AD641AP	AD	N/a	5	avai	250 MHz Demodulating Logarithmic Amplifier