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AD640BD-AD640BP-AD640JN-AD640JP
DC-Coupled Demodulating 120 MHz Logarithmic Amplifier
ATN OUT
ATN LO
ATN COM
SIG +IN
SIG –IN
ATN COM
COM
ATN INRG1RG0RG2
–VSBL1
+VS
LOG OUTLOG COM
SIG +OUT
SIG –OUT
BL2
ITCDC-Coupled Demodulating
120 MHz Logarithmic Amplifier
FEATURES
Complete, Fully Calibrated Monolithic System
Five Stages, Each Having 10 dB Gain, 350 MHz BW
Direct Coupled Fully Differential Signal Path
Logarithmic Slope, Intercept and AC Response are
Stable Over Full Military Temperature Range
Dual Polarity Current Outputs Scaled 1 mA/Decade
Voltage Slope Options (1 V/Decade, 100 mV/dB, etc.)
Low Power Operation (Typically 220 mW at 65 V)
Low Cost Plastic Packages Also Available
APPLICATIONS
Radar, Sonar, Ultrasonic and Audio Systems
Precision Instrumentation from DC to 120 MHz
Power Measurement with Absolute Calibration
Wide Range High Accuracy Signal Compression
Alternative to Discrete and Hybrid IF Strips
Replaces Several Discrete Log Amp ICs
PRODUCT DESCRIPTIONThe AD640 is a complete monolithic logarithmic amplifier. A single
AD640 provides up to 50 dB of dynamic range for frequencies
from dc to 120 MHz. Two AD640s in cascade can provide up to
95 dB of dynamic range at reduced bandwidth. The AD640 uses a
successive detection scheme to provide an output current propor-
tional to the logarithm of the input voltage. It is laser calibrated to
close tolerances and maintains high accuracy over the full military
temperature range using supply voltages from –4.5 V to –7.5 V.
The AD640 comprises five cascaded dc-coupled amplifier/limiter
stages, each having a small signal voltage gain of 10 dB and a –3 dB
bandwidth of 350 MHz. Each stage has an associated full-wave
detector, whose output current depends on the absolute value of its
input voltage. The five outputs are summed to provide the video
output (when low-pass filtered) scaled at 1 mA per decade (50 mA
per dB). On chip resistors can be used to convert this output cur-
rent to a voltage with several convenient slope options. A balanced
signal output at +50 dB (referred to input) is provided to operate
AD640s in cascade.
The logarithmic response is absolutely calibrated to within –1 dB
for dc or square wave inputs from –0.75 mV to –200 mV, with
an intercept (logarithmic offset) at 1 mV dc. An integral X10
attenuator provides an alternative input range of –7.5 mV to2 V dc. Scaling is also guaranteed for sinusoidal inputs.
The AD640B is specified for the industrial temperature range of
–40°C to +85°C and the AD640T, available processed to MIL-
STD-883B, for the military range of –55°C to +125°C. Both are
available in 20-lead side-brazed ceramic DIPs or leadless chip
carriers (LCC). The AD640J is specified for the commercial
temperature range of 0°C to +70°C, and is available in both
20-lead plastic DIP (N) and PLCC (P) packages.
This device is now available to Standard Military Drawing
(DESC) number 5962-9095501MRA and 5962-9095501M2A.
PRODUCT HIGHLIGHTSAbsolute calibration of a wideband logarithmic amplifier is
unique. The AD640 is a high accuracy measurement device,
not simply a logarithmic building block.Advanced design results in unprecedented stability over the
full military temperature range.The fully differential signal path greatly reduces the risk of
instability due to inadequate power supply decoupling and
shared ground connections, a serious problem with com-
monly used unbalanced designs.Differential interfaces also ensure that the appropriate ground
connection can be chosen for each signal port. They further
increase versatility and simplify applications. The signal input
impedance is ~500 kW in shunt with ~2 pF.The dc-coupled signal path eliminates the need for numerous
interstage coupling capacitors and simplifies logarithmic
conversion of subsonic signals.
(continued on page 4)
FUNCTIONAL BLOCK DIAGRAMREV.C
*Protected under U.S. patent number 4,990,803.
AD640–SPECIFICATIONS
DC SPECIFICATIONS
(VS = 65 V, TA = +258C, unless otherwise noted)
AC SPECIFICATIONS3 dB BANDWIDTH
LOGARITHMIC OUTPUTS
PACKAGE OPTION
NOTESLogarithms to base 10 are used throughout. The response is independent of the sign of VIN.2Attenuation ratio trimmed to calibrate intercept to 10 mV when in use. It has a temperature coefficient of +0.30%/°C.Overall gain is trimmed using a –200 mV square wave at 2 kHz, corrected for the onset of compression.The fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute temperature.Currents defined as flowing into Pin 14. See FUNDAMENTALS OF LOGARITHMIC CONVERSION for full explanation of scaling concepts. Slope is measured
by linear regression over central region of transfer function.The logarithmic intercept in dBV (decibels relative to 1 V) is defined as 20 LOG10 (VX/1 V).The zero-signal current is a function of temperature unless internal temperature compensation (ITC) pin is grounded.Operating in circuit of Figure 24 using –0.1% accurate values for RLA and RLB. Includes slope and nonlinearity errors. Input offset errors also included for
VIN >3 mV dc, and over the full input range in ac applications.Essentially independent of supply voltages.Using the circuit of Figure 27, using cascaded AD640s and offset nulling. Input is sinusoidal, 0 dBm in 50 W = 223 mV rms.For a sinusoidal signal (see EFFECT OF WAVEFORM ON INTERCEPT). Pin 8 on second AD640 must be grounded to ensure temperature stability of intercept
for dual AD640 system.Using the circuit of Figure 24, using single AD640 and offset nulling. Input is sinusoidal, 0 dBm in 50 W = 223 mV rms.Using the circuit of Figure 32, using cascaded AD640s and attenuator. Square wave input.
All min and max specifications are guaranteed, but only those in boldface are 100% tested on all production units. Results from those tests are used to calculate
outgoing quality levels.
Specifications subject to change without notice.
THERMAL CHARACTERISTICS
AD640
(VS = 65 V, TA = +258C, unless otherwise noted)
AD640
CHIP DIMENSIONS AND
BONDING DIAGRAMDimensions shown in inches and (mm).
ABSOLUTE MAXIMUM RATINGS*SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–7.5V
Input Voltage (Pin 1 or Pin 20 to COM) . . . .–3 V to +300 mV
Attenuator Input Voltage (Pin 5 to Pin 3/4) . . . . . . . . . . .–4 V
Storage Temperature Range D, E . . . . . . . . .–65°C to +150°C
Storage Temperature Range N, P . . . . . . . . .–65°C to +125°C
Ambient Temperature Range, Rated Performance
Industrial, AD640B . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Military, AD640T . . . . . . . . . . . . . . . . . . .–55°C to +125°C
Commercial, AD640J . . . . . . . . . . . . . . . . . . .0°C to +70°C
Lead Temperature Range (Soldering60sec) . . . . . . . .+300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
CONNECTION DIAGRAMS
20-Lead Ceramic DIP (D) Package 20-Lead PLCC (P) Package 20-Terminal Ceramic LCC (E) Package
20-Lead Plastic DIP (N) Package
ATN COMCKT COM
ATN COMATN LO
BL2
SIG –INSIG +INATN OUT
RG1
RG0
RG2
LOG OUT
SIG –OUTSIG +OUT
LOG COM
ATN IN
BL1
–VS
ITC
SIG –OUT
BL2
ITC
ATN LO
ATN COM
ATN COM
–VS
BL1
ATN IN
SIG –INSIG +IN
ATN OUT
CKT COM
RG1
RG0
RG2
LOG OUT
LOG COM
+VS
SIG +OUT1912310111213
ATN COMCKT COM
ATN COMATN LO
BL2
SIG –INSIG +INATN OUT
RG1
RG0
RG2
LOG OUT
SIG –OUTSIG +OUT
LOG COM
ATN IN
BL1
–VS
ITC
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
(continued from page 1)The low input offset voltage of 50 mV (200 mV max) ensures
good accuracy for low level dc inputs.Thermal recovery “tails,” which can obscure the response
when a small signal immediately follows a high level input,
have been minimized by special attention to design details.The noise spectral density of 2 nV/√Hz results in a noise floor of
~23 mV rms (–80 dBm) at a bandwidth of 100 MHz. The dy-
namic range using cascaded AD640s can be extended to 95 dB
by the inclusion of a simple filter between the two devices.
TEMPERATURE – 8C
SLOPE CURRENT – mAFigure 1.Slope Current, IY vs.
Temperature
POWER SUPPLY VOLTAGES – 6 Volts
INTERCEPT VOLTAGE – mV
0.985Figure 4.Intercept Voltage, VX, vs.
Supply Voltages
INPUT VOLTAGE – mV
(EITHER SIGN)
OUTPUT CURRENT – mA
ERROR – dBFigure 7.DC Logarithmic Transfer
Function and Error Curve for Single
AD640
TEMPERATURE – 8C
INTERCEPT – mV
0.85Figure 2.Intercept Voltage, VX, vs.
Temperature
TEMPERATURE – 8C
INTERCEPT – mVFigure 5.Intercept Voltage (Using
Attenuator) vs. Temperature
TEMPERATURE – 8C
ABSOLUTE ERROR – dBFigure 8.Absolute Error vs. Tem-
perature, VIN = 61 mV to 6100 mV
Figure 3.Slope Current, IY vs.
Supply Voltages
Figure 6.Input Offset Voltage
Deviation vs. Temperature
Figure 9.Absolute Error vs.
Temperature, Using Attenuator.
VIN = 610 mV to 61 V, Pin 8
Grounded to Disable ITC Bias
AD640
INPUT LEVEL – dBm
OUTPUT CURRENT – mA
30MHz
60MHz
90MHz
120MHzFigure 10.AC Response at 30 MHz, 60 MHz, 90 MHz and
120 MHz, vs. dBm Input (Sinusoidal Input)
FREQUENCY – MHz
SLOPE CURRENT – mA
0.806090120150Figure 11.Slope Current, IY, vs. Input Frequency
Figure 12.Baseband Pulse Response of Single AD640,
Inputs of 1 mV, 10 mV and 100 mV
Figure 13.Logarithmic Response and Linearity at 60 MHz,
TA for TA = –558C, +258C, +1258C
Figure 14.Intercept Level (dBm) vs. Frequency
(Cascaded AD640s – Sinusoidal Input)
Figure 15.Baseband Pulse Response of Cascaded
AD640s, Inputs of 0.2 mV, 2 mV, 20 mV and 200 mV
–Typical AC Performance Characteristics
CIRCUIT DESCRIPTIONThe AD640 uses five cascaded limiting amplifiers to approxi-
mate a logarithmic response to an input signal of wide dynamic
range and wide bandwidth. This type of logarithmic amplifier
has traditionally been assembled from several small scale ICs
and numerous external components. The performance of these
semidiscrete circuits is often unsatisfactory. In particular, the
logarithmic slope and intercept (see FUNDAMENTALS OF
LOGARITHMIC CONVERSION) are usually not very stable
in the presence of supply and temperature variations even after
laborious and expensive individual calibration. The AD640
employs high precision analog circuit techniques to ensure sta-
bility of scaling over wide variations in supply voltage and tem-
perature. Laser trimming, using ac stimuli and operating
conditions similar to those encountered in practice, provides fully
calibrated logarithmic conversion.
Each of the amplifier/limiter stages in the AD640 has a small
signal voltage gain of 10 dB (·3.162) and a –3 dB bandwidth of
350 MHz. Fully differential direct coupling is used throughout.
This eliminates the many interstage coupling capacitors usually
required in ac applications, and simplifies low frequency signal
processing, for example, in audio and sonar systems. The
AD640 is intended for use in demodulating applications. Each
stage incorporates a detector (a full wave transconductance
rectifier) whose output current depends on the absolute value of
its input voltage.
Figure 16 is a simplified schematic of one stage of the AD640.
All transistors in the basic cell operate at near zero collector to
base voltage and low bias currents, resulting in low levels of ther-
mally induced distortion. These arise when power shifts from one
set of transistors to another during large input signals. Rapid
recovery is essential when a small signal immediately follows a
large one. This low power operation also contributes signifi-
cantly to the excellent long-term calibration stability of the AD640.
The complete AD640, shown in Figure 17, includes two bias
regulators. One determines the small signal gain of the amplifier
stages; the other determines the logarithmic slope. These bias
regulators maintain a high degree of stability in the resulting
function by compensating for potentially large uncertainties
in transistor parameters, temperature and supply voltages. A
third biasing block is used to accurately control the logarithmic
intercept.
By summing the signals at the output of the detectors, a good
approximation to a logarithmic transfer function can be achieved.
The lower the stage gain, the more accurate the approximation,
but more stages are then needed to cover a given dynamic
range. The choice of 10 dB results in a theoretical periodic
Figure 16.Simplified Schematic of a Single AD640 Stage
deviation or ripple in the transfer function of –0.15 dB from the
ideal response when the input is either a dc voltage or a square
wave. The slope of the transfer function is unaffected by the
input waveform; however, the intercept and ripple are waveform
dependent (see EFFECT OF WAVEFORM ON INTERCEPT).
The input will usually be an amplitude modulated sinusoidal
carrier. In these circumstances the output is a fluctuating current at
twice the carrier frequency (because of the full wave detection)
whose average value is extracted by an external low-pass filter,
which recovers a logarithmic measure of the baseband signal.
Circuit OperationWith reference to Figure 16, the transconductance pair Q7, Q8
and load resistors R3 and R4 form a limiting amplifier having a
small signal gain of 10 dB, set by the tail current of nominally
2.18 mA at 27°C. This current is basically proportional to abso-
lute temperature (PTAT) but includes additional current to
compensate for finite beta and junction resistance. The limiting
output voltage is –180 mV at 27°C and is PTAT. Emitter fol-
lowers Q1 and Q2 raise the input resistance of the stage, provide
level shifting to introduce collector bias for the gain stage and
detectors, reduce offset drift by forming a thermally balanced
quad with Q7 and Q8 and generate the detector biasing across
resistors R1 and R2.
Transistors Q3 through Q6 form the full wave detector, whose
output is buffered by the cascodes Q9 and Q10. For zero input
Q3 and Q5 conduct only a small amount (a total of about
32 mA) of the 565 mA tail currents supplied to pairs Q3–Q4 and
Q5–Q6. This “pedestal” current flows in output cascode Q9 to
the LOG OUT node (Pin 14). When driven to the peak output
of the preceding stage, Q3 or Q5 (depending on signal polarity)
conducts lost of the tail current, and the output rises to 532 mA.
The LOG OUT current has thus changed by 500 mA as the
input has changed from zero to its maximum value. Since the
detectors are spaced at 10 dB intervals, the output increases by
ATN OUT
ATN LO
SIG +IN
SIG –IN
COMRG1RG0RG2
+VS
LOG OUTLOG COM
SIG +OUT
SIG –OUT
AD64050 mA/dB, or 1 mA per decade. This scaling parameter is
trimmed to absolute accuracy using a 2 kHz square wave. At
frequencies near the system bandwidth, the slope is reduced due
to the reduced output of the limiter stages, but it is still rela-
tively insensitive to temperature variations so that a simple ex-
ternal slope adjustment in restore scaling accuracy.
The intercept position bias generator (Figure 17) removes the
pedestal current from the summed detector outputs. It is ad-
justed during manufacture such that the output (flowing into
Pin 14) is 1 mA when a 2 kHz square-wave input of exactly10 mV is applied to the AD640. This places the dc intercept at
precisely 1 mV. The LOG COM output (Pin 13) is the comple-
ment of LOG OUT. It also has a 1 mV intercept, but with an
inverted slope of –1 mA/decade. Because its pedestal is very
large (equivalent to about 100 dB), its intercept voltage is not
guaranteed. The intercept positioning currents include a special
internal temperature compensation (ITC) term which can be
disabled by connecting Pin 8 to ground.
The logarithmic function of the AD640 is absolutely calibrated
to within –0.3 dB (or –15 mA) for 2 kHz square-wave inputs of1 mV to –100 mV, and to within –1 dB between –750 mV and200 mV. Figure 18 is a typical plot of the dc transfer function,
showing the outputs at temperatures of –55°C, +25°C and
+125°C. While the slope and intercept are seen to be little af-
fected by temperature, there is a lateral shift in the endpoints of
the “linear” region of the transfer function, which reduces the
effective dynamic range. The cause of this shift is explained in
Fundamentals of Logarithmic Conversion section.
INPUT VOLTAGE – mV
OUTPUT CURRENT – mA
+258C
ABSOLUTE ERROR – dBFigure 18.Logarithmic Output and Absolute Error vs. DC
or Square Wave Input at TA = –55°C, +25°C, Input Direct
to Pins 1 and 20
The on chip attenuator can be used to handle input levels 20 dB
higher, that is, from –7.5 mV to –2 V for dc or square wave
inputs. It is specially designed to have a positive temperature
coefficient and is trimmed to position the intercept at 10 mV dc
(or –24 dBm for a sinusoidal input) over the full temperature
range. When using the attenuator the internal bias compensa-
tion should be disabled by grounding Pin 8. Figure 19 shows
the output at –55°C, +25°C, +85°C and +125°C for a single
AD640 with the attenuator in use; the curves overlap almost
perfectly, and the lateral shift in the transfer function does not
occur. Therefore, the full dynamic range is available at all
Figure 19. Logarithmic Output and Absolute Error vs. DC
or Square Wave Input at TA = –55°C, +25°C, +85°C and
+125°C, Input via On-Chip Attenuator
roughly a square waveform. The signal path may be extended
using these outputs (see OPERATION OF CASCADED
AD640s). The logarithmic outputs from two or more AD640s
can be directly summed with full accuracy.
A pair of 1 kW applications resistors, RG1 and RG2 (Figure 17)
are accessed via Pins 15, 16 and 17. These can be used to con-
vert an output current to a voltage, with a slope of 1 V/decade
(using one resistor), 2 V/decade (both resistors in series) or
0.5 V/decade (both in parallel). Using all the resistors from two
AD640s (for example, in a cascaded configuration) ten slope
options from 0.25 V to 4 V/decade are available.
FUNDAMENTALS OF LOGARITHMIC CONVERSIONThe conversion of a signal to its equivalent logarithmic value
involves a nonlinear operation, the consequences of which can be
very confusing if not fully understood. It is important to realize
from the outset that many of the familiar concepts of linear
circuits are of little relevance in this context. For example, the
incremental gain of an ideal logarithmic converter approaches
infinity as the input approaches zero. Further, an offset at the
output of a linear amplifier is simply equivalent to an offset at
the input, while in a logarithmic converter it is equivalent to a
change of amplitude at the input—a very different relationship.
We assume a dc signal in the following discussion to simplify the
concepts; ac behavior and the effect of input waveform on cali-
bration are discussed later. A logarithmic converter having a
voltage input VIN and output VOUT must satisfy a transfer func-
tion of the form
VOUT = VY LOG (VIN/VX)Equation (1)
where Vy and Vx are fixed voltages which determine the scaling
of the converter. The input is divided by a voltage because the
argument of a logarithm has to be a simple ratio. The logarithm
must be multiplied by a voltage to develop a voltage output.
These operations are not, of course, carried out by explicit com-
putational elements, but are inherent in the behavior of the
converter. For stable operation, VX and VY must be based on
sound design criteria and rendered stable over wide temperature
and supply voltage extremes. This aspect of RF logarithmic
