AD6402ARS Fast Delivery |IC PHOENIX CO.,LIMITED

AD6402ARS ,IF Transceiver SubsystemCharacteristics:CTL1 11 18 DOUT28-lead SSOP package: θ = 109°C/W.JACFILT 12 17 DFILPCOFF 13 16PLLO ..
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AD640JN ,DC-Coupled Demodulating 120 MHz Logarithmic AmplifierSPECIFICATIONSS AModel AD640J AD640B AD640TParamet ..
AD640JP ,DC-Coupled Demodulating 120 MHz Logarithmic AmplifierFEATURES signal output at +50 dB (referred to input) is provided to operateComplete, Fully Calibrat ..
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AD6402ARS
IF Transceiver Subsystem
REV.0
IF Transceiver Subsystem
FEATURES
On-Chip Regulator
PLL Demodulator
On-Chip VCO
No Trims
Excellent Sensitivity
28-Lead SSOP Package
APPLICATIONS
DECT/PWT/WLAN
TDMA FM/FSK Systems
GENERAL DESCRIPTION
The AD6402 is a complete transceiver subsystem for use in
high bit rate radio systems employing FM or FSK modulation.
It is optimized for use in time domain multiple access (TDMA)
systems with communications rates of approximately 1 MBPS.
The AD6402 integrates key functions, including VCOs and a
low drop-out voltage regulator. The AD6402 operates directly
from an unregulated battery supply of 3.1 V to 4.5 V and pro-
vides a regulated voltage output which can be used for VCO
supply regulation on a companion RF chip such as the AD6401.
The AD6402 transceiver consists of a mixer, integrated IF
bandpass filter, IF limiter with RSSI detection, VCO, PLL
demodulator and a low dropout voltage regulator. On receive, it
downconverts an IF signal in the 110 MHz range to a second
IF frequency, this frequency being determined by the demodu-
lator reference divide ratios. It then filters, amplifies, and de-
modulates this signal. The AD6402 provides a filtered baseband
FUNCTIONAL BLOCK DIAGRAM
data output. On transmit, it accepts a Gaussian Frequency Shift
Keying (GFSK) baseband signal, low-pass filters the signal if
required using the on-chip op amp and modulates the IF VCO
by varying the bias voltage on an off-chip varactor diode used in
the tank circuit.
The AD6402 has multiple power-down modes to maximize
battery life. It operates over a temperature range of –25°C to
+85°C and is packaged in a JEDEC standard 28-lead small-
shrink outline (SSOP) surface-mount package.
AD6402–SPECIFICATIONS
RECEIVER
DEMODULATOR
DATA FILTER OP AMP
IF VCO
TRANSMIT FILTER OP AMP
POWER CONTROL
SUPPLY REGULATOR
POWER SUPPLY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
RECOMMENDED OPERATING CONDITIONS
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1 V–4.5 V
IFVCC1, IFVCC2, PLLVCC . . . . . . . . . . . . . . . . . . . .2.85 V
Operating Temperature Range . . . . . . . . . . .–25°C to +85°C
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5.5 V
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature, Soldering (60 sec) . . . . . . . . . . . .+300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended rating conditions for extended periods may affect device
reliability.
Thermal Characteristics:
28-lead SSOP package: θJA = 109°C/W.
ORDERING GUIDE
PIN CONFIGURATION
TXOUTB
IFIN
IFVCC1
REFSEL
TXOUT
MODOUT
FMMOD2
FMMOD1
IFVCC2
RSSI
IFGNDVCOGND
VCO
VREG
VBAT
CTL3
CTL2SLREF
PLLVCC
PLLGND
CTL1
CFILT
COFF
REXT
DOUT
REFIN
PLLOUT
DFILP
PIN FUNCTION DESCRIPTIONS
AD6402
VCO
1nF
150pF
VCCI
Figure 1.
OVERVIEW
The AD6402 forms the basis of a highly integrated RF trans-
ceiver with the benefits of increased sensitivity and wide dy-
namic range that a dual-conversion architecture provides. The
IC contains a low dropout voltage regulator to isolate the IF and
demodulator VCOs from variation in the battery voltage, such
as power-supply transients caused by the PA. The AD6402 also
provides control circuitry that allows subcircuits to be turned off
and on as necessary to minimize power consumption.
Operation During Receive
The AD6402 contains the second mixer, integrated second-IF
bandpass filter, logarithmic-limiting amplifier, and PLL de-
modulator. A SAW IF bandpass filter is usually required at the
IF input in order to provide channel selectivity.
The placement of the SAW filter in the signal path between
the AD6402 and the RF section and the partitioning of the
receiver’s RF and IF receive circuits minimizes the leakage
around the SAW filter and maximizes the RF to IF isolation.
The output of the SAW filter enters the AD6402 via the second
downconversion mixer. This mixer is a high gain, doubly-
balanced Gilbert-cell type. The mixer downconverts the signal
to the second IF, which is 1.5 × or 2.5 × the reference frequency.
This multiple is determined by the state of the REFSEL pin. An
on-chip two section bandpass filter provides additional selectiv-
ity to provide attenuation of adjacent channels. The VCO con-
trol voltage output of the PLL demodulator tunes this filter to
the second IF.
The bandpass filter’s output enters a successive-detection loga-
rithmic-limiting IF amplifier. The RSSI detectors are distrib-
uted across the entire IF strip, including the mixer, and provide
80 dB RSSI range. The IF strip’s limiting gain also exceeds 80
dB. The RSSI signal is low-pass filtered and proceeds off-chip
to the baseband subsystem. The limited output of the logarith-
mic amplifier enters a PLL demodulator, which provides de-
modulation of the received signal. The PLL uses an integrated
VCO with no external components.
Operation During Transmit
The transmit signal path consists of a low-pass filter that can be
user configured for antialiasing of a baseband transmit signal.
An IF VCO, which should be tuned to a frequency equal to the
receive IF frequency plus the desired demodulator input fre-
equal to the sum of the IF frequency plus the frequency of the
PLL demodulator input as defined by the reference clock
divider ratios.
The transmit IF VCO uses an external tank circuit. This signal
is upconverted to the transmit frequency in the RF mixer sec-
tion of the radio. Using a transmit IF VCO prevents two prob-
lems: feedback from the PA at the RF frequency does not cause
distortion in the modulating circuit because the frequencies are
widely separated and the IF tank circuit can be optimized for
modulation linearity.
The output of the transmit VCO passes through buffer amplifier
and leaves the AD6402 via an optional LC filter between the RF
and IF ICs. The output of the LC filter may then be fed to a
transmit upconversion mixer for conversion to the final RF
frequency.
Onboard Voltage Regulation
The AD6402 contains a low dropout voltage regulator to spe-
cifically isolate the VCOs and synthesizer from the voltage
“kick” that occurs when a power amplifier switches on and the
battery voltage abruptly drops. The AD6402 uses an integral
vertical PNP pass transistor.
The regulator in the AD6402 IF IC supplies the voltage for the
VCOs on both the RF section and AD6402. The other sections
of the AD6402 should be powered from an independently regu-
lated source at 2.85 V. Since the VCOs are isolated from this
source, possible problems due to VCO supply pushing are con-
siderably reduced.
Frequency Control
The AD6402 requires an external synthesizer to provide the
control voltages for the tank circuit of the IF VCO. Normally
this will be the IF section of a dual synthesizer controlling both
IF and RF frequency generation.
It is recommended that the VCO on the RF section implement
the channel selection on transmit and receive; the VCO on the
AD6402 may therefore operate at a fixed frequency. This ac-
complishes two goals: first, the IF VCO being modulated can be
optimized for modulation linearity and the RF VCO can be
optimized for tuning range, and second, feedback from the PA
at will not couple into the modulating circuit to cause spurious
responses.
All key sections of the AD6402 may be powered up or down as
Table I.Power Management Functionality
Figure 2.Power Management Scheme
The AD6402 has six operating modes: SLEEP, STANDBY,
RXLOCK, RXDMOD, TRANSMIT and RXLOCKP. These
are summarized in Table I. The blocks referred to in Table I are
shown also in Figure 4. These modes are described as follows:
SLEEP:The entire device is shut down.
STANDBY:All functions except the regulator are shut down.
RXLOCK:The device locks to a local reference clock using
the lock PLL. The lock charge pump and divid-
ers are powered up. The VCO is also powered up.
RXDMOD:In this mode the lock charge pump and loop
dividers are shut down. The receive mixer, IF strip,
reference and demodulator are powered up.
TRANSMIT:This mode enables the VCO and transmit op
amp. The reference and regulator are also enabled.
RXLOCKP:This mode may be used in a “prior to” timeslot,
i.e., the slot before the actual active receive
timeslot. In this mode, after lock has been
achieved in the RXLOCK mode, the receive
mixer, VCO and IF strip may then be indepen-
dently powered up from the demodulator loop.
This can result is power savings, since the de-
modulator may be powered down during the
IF VCO lock acquisition time.
AD6402
Demodulator Operation
The PLL itself uses two loops: one for rapid frequency acquisi-
tion and a second for demodulation. The first, or frequency-
acquisition loop, locks the VCO to a noninteger multiple of the
system clock, either 3/2 or 5/2 (using one fixed /2 and one pro-
grammable /3 or /5 divider). This allows not only a choice of IF
and system clocks but also prevents blocking of the receiver by
keeping integer multiples of the system clock out of the IF
passband.
Once locked, this loop voltage is stored on an external capacitor
and this sets the free-running frequency of the VCO during
demodulation. The first loop is opened and, using the second
loop and phase detector, the PLL compares the free-running
frequency of its VCO to the frequency of the incoming IF. The
VCO is then fast frequency locked, and slow phase locked to the
incoming IF. Preconditioning of the PLL to the local reference
clock facilitates the fast frequency lock to the received IF. The
PLL now generates a baseband voltage proportional to the fre-
quency deviation of the received signal.
The demodulator uses a third-order PLL to track the incoming
modulation signal. A simplified diagram of the demodulator is
shown in Figures 3a and 3b. The loop bandwidth and damping
factor can be adjusted by changing the values of C and R as
indicated. An internal pole is present on the demodulator loop
at approximately 9 MHz. For a loop ωn of 800 kHz, values of
910 pF and 330 Ω respectively are optimum. The loop band-
width will approximately scale inversely as the square root of the
value of C. To preserve a satisfactory damping factor, R should
be adjusted linearly with the loop bandwidth. At low loop band-
widths however the value of C offset must also be increased to
enable the loop to lock to the reference frequency during prior
to receive time slots.
APPLICATIONS
The AD6402 is optimized for use in applications where a data
rate of the order of 1 megabit per second is required and the
modulation scheme employed is constant envelope, i.e., FM or
FSK. Because the demodulator uses a track and hold technique
that locks to an externally supplied reference clock, the device is
optimized for use in TDMA systems. If used in continuous
demodulation applications, the dc offset hold voltage on the
demodulator differential amplifier will ultimately leak away,
COFFSET
VCO
220
Figure 3a.Demodulator Block Diagram (Lock Mode)
Figure 3b.Demodulator Block Diagram (Dmod Mode)
timeslot, thereby enabling a very accurate dc offset compensa-
tion of system frequency errors.
The on-chip IF filter has been designed to provide some rejec-
tion of adjacent channel signals for channel bandwidths in the
1 MHz–2 MHz range. This filter has the benefit of reducing the
contribution of broadband noise through the IF strip, hence
improving the overall sensitivity of the receiver for a given
demodulator output signal to noise ratio.
It is also possible to use the AD6402 in applications where non-
constant envelope modulation schemes are used, such as QPSK.
In these applications the amplitude information will be lost
through the limiting action of the IF strip, but in certain appli-
cations, sufficient eye-opening will be observed in the demodu-
lated signal to allow the use of hard decision bit-slicers as in the
FM or FSK case. The actual performance of the subsystem in
the presence of a QPSK signal will depend on factors such as bit
rate, modulation index and BT employed.
Figure 4 shows the RSSI response to a DECT signal at the IF
port. It can be seen from the plot that the AD6402 can detect
signals below –85 dBm and continues to detect linearly up to
and above –5 dBm.
INPUT POWER – dBm
RSSI – V
Figure 4.RSSI Response
Figure 5 shows an implementation for a DECT IF subsystem.
DECT is a 1.152 megabit/second radio, employing Gaussian
FSK modulation at a BT = 0.5 and uses a channel spacing of

Partno	Mfg	Dc	Qty	Available	Descript
AD6402ARS	AD	N/a	2595	avai	IF Transceiver Subsystem