AD630KN ,Balanced Modulator/DemodulatorSPECIFICATIONSSModel AD630J/A AD630K/B AD630SMin Typ Max Min Typ Max Min Ty ..
AD630SD ,Balanced Modulator/Demodulatorapplications requiring wide dynamic range.When used as a synchronous demodulator in a lock-in ampli ..
AD630SD/883B , Balanced Modulator/Demodulator
AD6311 , 1/8- to 1/16 Duty VFD Controller/Driver
AD632AD ,Internally Trimmed Precision IC Multiplierspecifications and a fully differential high(AD632T) are guaranteed over the extended temperature r ..
AD632AH ,Internally Trimmed Precision IC MultiplierSPECIFICATIONSSAD632A AD632B AD632S AD632TModel Min Typ Max Min Typ Max Min Typ Max Min Typ Max Uni ..
AD9985ABSTZ-110 , 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
AD9985ABSTZ-110 , 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
AD9985AKSTZ-110 , 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
AD9985AKSTZ-110 , 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
AD9985BSTZ-110 ,110 MSPS/140 MSPS Analog Interface for Flat Panel DisplaysGENERAL DESCRIPTION The AD9985 is a complete 8-bit, 140 MSPS, monolithic analog to 140 MHz. PLL clo ..
AD9985KSTZ-110 ,110 MSPS/140 MSPS Analog Interface for Flat Panel DisplaysSpecifications.... 3 2-Wire Serial Control Register Detail Chip Identification... 19 Explanation of ..
AD630AD-AD630BD-AD630JN-AD630KN-AD630SD
Balanced Modulator/Demodulator
FUNCTIONAL BLOCK DIAGRAMREV.C
Balanced Modulator/Demodulator
PRODUCT DESCRIPTIONThe AD630 is a high precision balanced modulator which com-
bines a flexible commutating architecture with the accuracy and
temperature stability afforded by laser wafer trimmed thin-film
resistors. Its signal processing applications include balanced
modulation and demodulation, synchronous detection, phase
detection, quadrature detection, phase sensitive detection,
lock-in amplification and square wave multiplication. A network
of on-board applications resistors provides precision closed loop
gains of ±1 and ±2 with 0.05% accuracy (AD630B). These
resistors may also be used to accurately configure multiplexer
gains of +1, +2, +3 or +4. Alternatively, external feedback may
be employed allowing the designer to implement his own high
gain or complex switched feedback topologies.
The AD630 may be thought of as a precision op amp with two
independent differential input stages and a precision comparator
which is used to select the active front end. The rapid response
time of this comparator coupled with the high slew rate and fast
settling of the linear amplifiers minimize switching distortion. In
addition, the AD630 has extremely low crosstalk between chan-
nels of –100 dB @ 10 kHz.
The AD630 is intended for use in precision signal processing
and instrumentation applications requiring wide dynamic range.
When used as a synchronous demodulator in a lock-in amplifier
configuration, it can recover a small signal from 100 dB of inter-
fering noise (see lock-in amplifier application). Although optimized
for operation up to 1 kHz, the circuit is useful at frequencies up
to several hundred kilohertz.
Other features of the AD630 include pin programmable frequency
compensation, optional input bias current compensation resis-
tors, common-mode and differential-offset voltage adjustment,
and a channel status output which indicates which of the two
differential inputs is active. This device is now available to Stan-
dard Military Drawing (DESC) numbers 5962-8980701RA and
5962-89807012A.
PRODUCT HIGHLIGHTSThe configuration of the AD630 makes it ideal for signal
processing applications such as: balanced modulation and
demodulation, lock-in amplification, phase detection, and
square wave multiplication.The application flexibility of the AD630 makes it the best
choice for many applications requiring precisely fixed gain,
switched gain, multiplexing, integrating-switching functions,
and high-speed precision amplification.The 100 dB dynamic range of the AD630 exceeds that of any
hybrid or IC balanced modulator/demodulator and is compa-
rable to that of costly signal processing instruments.The op-amp format of the AD630 ensures easy implementa-
tion of high gain or complex switched feedback functions.
The application resistors facilitate the implementation of
most common applications with no additional parts.The AD630 can be used as a two channel multiplexer with
gains of +1, +2, +3 or +4. The channel separation of
100 dB @ 10 kHz approaches the limit which is achievable
with an empty IC package.The AD630 has pin-strappable frequency compensation (no
external capacitor required) for stable operation at unity gain
without sacrificing dynamic performance at higher gains.Laser trimming of comparator and amplifying channel offsets
eliminates the need for external nulling in most cases.
FEATURES
Recovers Signal from +100 dB Noise
2 MHz Channel Bandwidth
45 V/�s Slew Rate
–120 dB Crosstalk @ 1 kHz
Pin Programmable Closed Loop Gains of �1 and �2
0.05% Closed Loop Gain Accuracy and Match
100 �V Channel Offset Voltage (AD630BD)
350 kHz Full Power Bandwidth
Chips Available
AD630–SPECIFICATIONS
ORDERING GUIDE
(@ + 25�C and �VS = �15 V unless otherwise noted)NOTESIf one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply.These parameters are guaranteed but not tested for J and K grades. For A, B and S grades they are tested.ISINK @ VOL = (–VS + 1) volt is typically 4 mA.Pin 12 Open. Slew rate with Pins 12 and 13 shorted is typically 35 V/µs.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGSSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . .600 mW
Output Short Circuit to Ground . . . . . . . . . . . . . . . .Indefinite
Storage Temperature, Ceramic Package . . . .–65°C to +150°C
Storage Temperature, Plastic Package . . . . . .–55°C to +125°C
Lead Temperature Range (Soldering, 10 sec ) . . . . . . .+300°C
Max Junction Temperature . . . . . . . . . . . . . . . . . . . . .+150°C
THERMAL CHARACTERISTICS
PIN CONFIGURATIONS
20-Lead DIP (D-20 and N-20)
20-Contact LCC (E-20A) 19123
DIFF OFF ADJ
CM OFF ADJ
CM OFF ADJ
CHANNEL STATUS B/A
–VS
CH B+
RIN B
DIFFOFF ADJCH A+
CH A
CH B
SEL B
SEL A
COMP
OUTTypical Performance CharacteristicsFigure 2.Output Voltage vs.
Resistive Load
Figure 3.Output Voltage Swing
vs. Supply Voltage
CHIP METALIZATION AND PINOUTDimensions shown in inches and (mm).
Contact factory for latest dimensions
CHIP AVAILABILITYThe AD630 is available in laser trimmed, passivated chip form.
The figure shows the AD630 metalization pattern, bonding pads
and dimensions. AD630 chips are available; consult factory for
details.
Figure 1.Output Voltage vs.
Frequency
51015
SUPPLY VOLTAGE – �V
OUTPUT VOLTAGE
AD630–Typical Performance CharacteristicsFigure 7.Channel-to-Channel Switch-
Settling Characteristic
Figure 9.Large Signal Inverting
Step Response
TWO WAYS TO LOOK AT THE AD630The functional block diagram of the AD630 (see page 1) also
shows the pin connections of the internal functions. An alternative
architectural diagram is shown in Figure 10. In this diagram, the
individual A and B channel preamps, the switch, and the inte-
grator output amplifier are combined in a single op amp. This
amplifier has two differential input channels, only one of which
is active at a time.
+VS
SEL B
SEL A
B/A
–VSFigure 10.Architectural Block Diagram
HOW THE AD630 WORKSThe basic mode of operation of the AD630 may be more easy to
recognize as two fixed gain stages which may be inserted into the
signal path under the control of a sensitive voltage comparator.
When the circuit is switched between inverting and noninverting
gain, it provides the basic modulation/demodulation function. The
AD630 is unique in that it includes Laser-Wafer-Trimmed thin-
film feedback resistors on the monolithic chip. The configuration
shown in Figure 11 yields a gain of ±2 and can be easily changed to
Figure 11.AD630 Symmetric Gain (±2)
When channel B is selected, the resistors RA and RF are con-
nected for inverting feedback as shown in the inverting gain
configuration diagram in Figure 12. The amplifier has sufficient
loop gain to minimize the loading effect of RB at the virtual
ground produced by the feedback connection. When the sign of
the comparator input is reversed, input B will be deselected and
A will be selected. The new equivalent circuit will be the nonin-
verting gain configuration shown below. In this case RA will appear
across the op-amp input terminals, but since the amplifier drives
this difference voltage to zero the closed loop gain is unaffected.
The two closed loop gain magnitudes will be equal when RF/RA
= 1 + RF/RB, which will result from making RA equal to RFRB/
(RF + RB) the parallel equivalent resistance of RF and RB.
The 5k and the two 10k resistors on the AD630 chip can be
used to make a gain of two as shown here. By paralleling the
10k resistors to make RF equal 5k and omitting RB the circuit
can be programmed for a gain of ±1 (as shown in Figure 18a).
These and other configurations using the on chip resistors
Figure 8.Small Signal Noninverting
Step Response
Figure 12.Inverting Gain Configuration
Figure 13.Noninverting Gain Configuration
CIRCUIT DESCRIPTIONThe simplified schematic of the AD630 is shown in Figure 14.
It has been subdivided into three major sections, the comparator,
the two input stages and the output integrator. The comparator
consists of a front end made up of Q52 and Q53, a flip-flop load
formed by Q3 and Q4, and two current steering switching cells
Q28, Q29 and Q30, Q31. This structure is designed so that a
differential input voltage greater than 1.5 mV in magnitude
applied to the comparator inputs will completely select one the
switching cells. The sign of this input voltage determine which
of the two switching cells is selected.
Figure 14.AD630 Simplified Schematic
The collectors of each switching cell connect to an input trans-
conductance stage. The selected cell conveys bias currents i22
and i23 to the input stage it controls, causing it to become active.
The deselected cell blocks the bias to its input stage which, as a
consequence, remains off.
The structure of the transconductance stages is such that they
present a high impedance at their input terminals and draw no
bias current when deselected. The deselected input does not
interfere with the operation of the selected input insuring maxi-
mum channel separation.
Another feature of the input structure is that it enhances the
faster the output signal will move. This feature helps insure
rapid, symmetric settling when switching between inverting and
noninverting closed loop configurations.
The output section of the AD630 includes a current mirror-load
(Q24 and Q25), an integrator-voltage gain stage (Q32), and
complementary output buffer (Q44 and Q74). The outputs of
both transconductance stages are connected in parallel to the
current mirror. Since the deselected input stage produces no
output current and presents a high impedance at its outputs,
there is no conflict. The current mirror translates the differential
output current from the active input transconductance amplifier
into single ended form for the output integrator. The comple-
mentary output driver then buffers the integrator output pro-
duce a low impedance output.
OTHER GAIN CONFIGURATIONSMany applications require switched gains other than the ±1 and
±2 which the self-contained applications resistors provide. The
AD630 can be readily programmed with three external resistors
over a wide range of positive and negative gain by selecting and
RB and RF to give the noninverting gain 1 + RF/RB and subsequent
RA to give the desired inverting gain. Note that when the inverting
magnitude equals the noninverting magnitude, the value of RA is
found to be RB RF/(RB + RF). That is, RA should equal the parallel
combination of RB and RF to match positive and negative gain.
The feedback synthesis of the AD630 may also include reactive
impedance. The gain magnitudes will match at all frequencies if
the A impedance is made to equal the parallel combination of
the B and F impedances. Essentially the same considerations
apply to the AD630 as to conventional op-amp feedback circuits.
Virtually any function which can be realized with simple nonin-
verting “L network” feedback can be used with the AD630. A
common arrangement is shown in Figure 15. The low frequency
gain of this circuit is 10. The response will have a pole (–3 dB)
at a frequency f � 1/(2 π 100 kΩC) and a zero (3 dB from the
high frequency asymptote) at about 10 times this frequency.
The 2k resistor in series with each capacitor mitigates the load-
ing effect on circuitry driving this circuit, eliminates stability
problems, and has a minor effect on the pole-zero locations.
As a result of the reactive feedback, the high frequency components
of the switched input signal will be transmitted at unity gain
Figure 15. AD630 with External Feedback
while the low frequency components will be amplified. This
arrangement is useful in demodulators and lock-in amplifiers. It
increases the circuit dynamic range when the modulation or
AD630
SWITCHED INPUT IMPEDANCEThe noninverting mode of operation is a high input impedance
configuration while the inverting mode is a low input impedance
configuration. This means that the input impedance of the
circuit undergoes an abrupt change as the gain is switched un-
der control of the comparator. If gain is switched when the
input signal is not zero, as it is in many practical cases, a tran-
sient will be delivered to the circuitry driving the AD630. In
most applications, this will require the AD630 circuit to be
driven by a low impedance source which remains “stiff “ at high
frequencies. Generally this will be a wideband buffer amplifier.
FREQUENCY COMPENSATIONThe AD630 combines the convenience of internal frequency
compensation with the flexibility of external compensation by
means of an optional self-contained compensation capacitor.
In gain of ±2 applications the noise gain which must be addressed
for stability purposes is actually 4. In this circumstance, the
phase margin of the loop will be on the order of 60° without the
optional compensation. This condition provides the maximum
bandwidth and slew-rate for closed-loop gains of |2| and above.
When the AD630 is used as a multiplexer, or in other configura-
tions where one or both inputs are connected for unity gain
feedback, the phase margin will be reduced to less than 20°.
This may be acceptable in applications where fast slewing is a
first priority, but the transient response will not be optimum.
For these applications, the self-contained compensation capaci-
tor may be added by connecting Pin 12 to Pin 13. This connec-
tion reduces the closed loop bandwidth somewhat, and improves
the phase margin.
For intermediate conditions, such as gain of ±1 where loop
attenuation is 2, use of the compensation should be determined
by whether bandwidth or settling response must be optimized.
The optional compensation should also be used when the AD630
is driving capacitive loads or whenever conservative frequency
compensation is desired.
OFFSET VOLTAGE NULLINGThe offset voltages of both input stages and the comparator
have been pretrimmed so that external trimming will only be
required in the most demanding applications. The offset adjust-
ment of the two input channels is accomplished by means of a
differential and common-mode scheme. This facilitates fine
adjustment of system errors in switched gain applications. With
system input tied to 0 V, and a switching or carrier waveform
applied to the comparator, a low level square wave will appear at
the output. The differential offset adjustment pot can be used
to null the amplitude of this square wave (Pins 3 and 4). The
common-mode offset adjustment can be used to zero the re-
sidual dc output voltage (Pins 5 and 6). These functions should
be implemented using 10k trim pots with wipers connected
directly to Pin 8 as shown in Figures 18a and 18b.
CHANNEL STATUS OUTPUTThe channel status output, Pin 7, is an open collector output
referenced to –VS which can be used to indicate which of the
two input channels is active. The output will be active (pulled
low) when Channel A is selected. This output can also be used
to supply positive feedback around the comparator. This pro-
because the open collector channel status output inverts the
output sense of the internal comparator.
Figure 16.Comparator Hysteresis
The channel status output may be interfaced with TTL inputs
as shown in Figure 17. This circuit provides appropriate level
shifting from the open-collector AD630 channel status output to
TTL inputs.
Figure 17.Channel Status—TTL Interface
APPLICATIONS: BALANCED MODULATORPerhaps the most commonly used configuration of the AD630 is
the balanced modulator. The application resistors provide pre-
cise symmetric gains of ±1 and ±2. The ±1 arrangement is
shown in Figure 18a and the ±2 arrangement is shown in Figure
18b. These cases differ only in the connection of the 10k feed-
back resistor (Pin 14) and the compensation capacitor (Pin 12).
Note the use of the 2.5 kΩ bias current compensation resistors
in these examples. These resistors perform the identical function
in the ±1 gain case. Figure 19 demonstrates the performance of
the AD630 when used to modulate a 100 kHz square wave
carrier with a 10 kHz sinusoid. The result is the double side-
band suppressed carrier waveform.
These balanced modulator topologies accept two inputs, a signal
(or modulation) input applied to the amplifying channels, and a
reference (or carrier) input applied to the comparator.
