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AD628AR-AD628ARM
High Common-Mode Voltage Programmable Gain Difference Amplifier
High Common-Mode Voltage
Programmable Gain Difference Amplifier
Rev. C
FEATURES
High common-mode input voltage range
±120 V at VS = ±15 V
Gain range 0.1 to 100
Operating temperature range: −40°C to ±85°C
Supply voltage range
Dual supply: ±2.25 V to ±18 V
Single supply: 4.5 V to 36 V
Excellent ac and dc performance
Offset temperature stability RTI: 10 µV/°C max
Offset: ±1.5 V mV max
CMRR RTI: 75 dB min, dc to 500 Hz, G = +1
APPLICATIONS
High voltage current shunt sensing
Programmable logic controllers
Analog input front end signal conditioning
+5 V, +10 V, ±5 V, ±10 V and 4 to 20 mA
Isolation
Sensor signal conditioning
Power supply monitoring
Electrohydraulic control
Motor control
GENERAL DESCRIPTION The AD628 is a precision difference amplifier that combines
excellent dc performance with high common-mode rejection
over a wide range of frequencies. When used to scale high
voltages, it allows simple conversion of standard control
voltages or currents for use with single-supply ADCs. A
wideband feedback loop minimizes distortion effects due to
capacitor charging of ∑-∆ ADCs.
A reference pin (VREF) provides a dc offset for converting
bipolar to single-sided signals. The AD628 converts +5 V, +10 V,
±5 V, ±10 V, and 4 to 20 mA input signals to a single-ended
output within the input range of single-supply ADCs.
The AD628 has an input common-mode and differential
mode operating range of ±120 V. The high common-mode
input impedance makes the device well suited for high voltage
measurements across a shunt resistor. The buffer amplifier’s
inverting input is available for making a remote Kelvin
connection.
FUNCTIONAL BLOCK DIAGRAM
REXT1REXT2+VS
–VS
+IN
–IN
VREF
CFILT02992-C
Figure 1.
CMRR (dB)
FREQUENCY (Hz)
100101k10k100k02992-C-002
Figure 2. CMRR vs. Frequency of the AD628
A precision 10 kΩ resistor connected to an external pin is
provided for either a low-pass filter or to attenuate large
differential input signals. A single capacitor implements a low-
pass filter. The AD628 operates from single and dual supplies and
is available in an 8-lead SOIC or MSOP package. It operates over
the standard industrial temperature range of −40°C to +85°C.
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Typical Performance Characteristics.............................................9
Test Circuits.....................................................................................13
Theory of Operation......................................................................14
Applications.....................................................................................15
Gain Adjustment.........................................................................15
Input Voltage Range...................................................................15
Voltage Level Conversion..........................................................16
Current Loop Receiver...............................................................17
Monitoring Battery Voltages.....................................................17
Filter Capacitor Values...............................................................18
Kelvin Connection.....................................................................18
Outline Dimensions.......................................................................19
Ordering Guide...........................................................................19
REVISION HISTORY
4/04—Data Sheet Changed from Rev. B to Rev. C Updated Format.................................................................Universal
Changes to Specifications...............................................................3
Changes to Absolute Maximum Ratings......................................7
Changes to Figure 3.........................................................................7
Changes to Figure 26.....................................................................13
Changes to Figure 27.....................................................................13
Changes to Theory of Operation................................................14
Changes to Figure 29.....................................................................14
Changes to Table 5.........................................................................15
Changes to Gain Adjustment Section.........................................15
Added the Input Voltage Range Section.....................................15
Added Figure 30............................................................................15
Added Figure 31............................................................................15
Changes to Voltage Level Conversion Section..........................16
Changes to Figure 32.....................................................................16
Changes to Table 6.........................................................................16
Changes to Figure 33 and Figure 34............................................17
Changes to Figure 35.....................................................................18
Changes to Kelvin Connection Section......................................18
6/03—Data Sheet Changed from Rev. A to Rev. B Changes to General Description...................................................1
Changes to Specifications...............................................................2
Changes to Ordering Guide...........................................................4
Changes to TPCs 4, 5, and 6...........................................................5
Changes to TPC 9............................................................................6
Updated Outline Dimensions......................................................14
1/03—Data Sheet Changed from Rev. 0 to Rev. A Change to Ordering Guide.............................................................4
11/02—Rev. 0: Initial Version SPECIFICATIONS TA = 25°C, VS = ±15 V, RL = 2 kΩ, REXT1 = 10 kΩ, REXT2 = ∞, VREF = 0 unless otherwise noted.
Table 1. To use a lower gain, see the Gain Adjustment section.
2The addition of the difference amp’s and output amp’s offset voltage does not exceed this specification.
TA = 25°C, VS = +5 V, RL = 2 kΩ, REXT1 = 10 kΩ, REXT2 = ∞, VREF = +2.5 unless otherwise noted.
Table 2.
To use a lower gain, see the Gain Adjustment section.
2 The addition of the difference amp’s and output amp’s offset voltage does not exceed this specification.
3 Greater values of voltage are possible with greater or lesser values of VREF.
ABSOLUTE MAXIMUM RATINGS
Table 3. Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
When using ±12 V supplies or higher (see the Input Voltage Range section).
POW
ISSIPA
TION1.2
AMBIENT TEMPERATURE (°C)02992-C-003
Figure 3. Maximum Power Dissipation vs. Temperature
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
+IN
–VS
VREF
CFILT02992-C-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions TYPICAL PERFORMANCE CHARACTERISTICS
% OF UNITS
INPUT OFFSET VOLTAGE (mV)02992-C-005
Figure 5. Typical Distribution of Input Offset Voltage,
VS = ±15 V, SOIC Package
% OF UNITS
CMRR (dB)02992-C-006
Figure 6. Typical Distribution of Common-Mode Rejection, SOIC Package
CMRR (dB)
FREQUENCY (Hz)
100101k10k100k02992-C-007
Figure 7. CMRR vs. Frequency
RR (dB)
0.11101001k10k100k1M
FREQUENCY (Hz)02992-C-008
Figure 8. PSRR vs. Frequency, Single and Dual Supplies
VOLTA
GE N
OISE D
ITY (
V/ H
1000101001k10k100k
FREQUENCY (Hz)02992-C-009
Figure 9. Voltage Noise Spectral Density, RTI, VS = ±15 V
VOLTA
GE N
OISE D
ITY (
V/ H
1000101001k10k100k
FREQUENCY (Hz)02992-C-010
Figure 10. Voltage Noise Spectral Density, RTI, VS = ±2.5 V
02992-C-011
TIME (Sec)
ISE (
V/D
IV)Figure 11. 0.1 Hz to 10 Hz Voltage Noise, RTI
GAIN (
1001k10k100k1M10M
FREQUENCY (Hz)02992-C-012
Figure 12. Small Signal Frequency Response,
VOUT = 200 mV p-p, G = +0.1, +1, +10, and +100
GAIN (1001k10k100k1M
FREQUENCY (Hz)02992-C-013
Figure 13. Large Signal Frequency Response,
VOUT = 20 V p-p, G = +0.1, +1, +10, and +100
% OF D
EVIC12345678910
GAIN ERROR (ppm)02992-C-014
Figure 14. Typical Distribution of +1 Gain Error
COM
ON-
ODE VOLTAGE (
VS (±V)010152002992-C-015
Figure 15. Common-Mode Operating Range vs.
Power Supply Voltage for Three Temperatures
02992-C-016
OUTPUT VOLTAGE (V)
OUTP
UT E
RROR (Figure 16. Normalized Gain Error vs. VOUT, VS = ±15 V
