AD625AD-AD625BD-AD625CD-AD625JN-AD625KN-AD625SD Fast Delivery |IC PHOENIX CO.,LIMITED

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AD625AD-AD625BD-AD625CD-AD625JN-AD625KN-AD625SD
Programmable Gain Instrumentation Amplifier
FUNCTIONAL BLOCK DIAGRAM
REV.DProgrammable Gain
Instrumentation Amplifier
FEATURES
User Programmed Gains of 1 to 10,000
Low Gain Error: 0.02% Max
Low Gain TC: 5 ppm/�C Max
Low Nonlinearity: 0.001% Max
Low Offset Voltage: 25 �V
Low Noise 4 nV/√Hz (at 1 kHz) RTI
Gain Bandwidth Product: 25 MHz
16-Lead Ceramic or Plastic DIP Package,
20-Terminal LCC Package
Standard Military Drawing Available
MlL-Standard Parts Available
Low Cost
PRODUCT DESCRIPTION
The AD625 is a precision instrumentation amplifier specifically
designed to fulfill two major areas of application: 1) Circuits re-
quiring nonstandard gains (i.e., gains not easily achievable with
devices such as the AD524 and AD624). 2) Circuits requiring a
low cost, precision software programmable gain amplifier.
For low noise, high CMRR, and low drift the AD625JN is the
most cost effective instrumentation amplifier solution available.
An additional three resistors allow the user to set any gain from
1 to 10,000. The error contribution of the AD625JN is less than
0.05% gain error and under 5 ppm/°C gain TC; performance
limitations are primarily determined by the external resistors.
Common-mode rejection is independent of the feedback resistor
matching.
A software programmable gain amplifier (SPGA) can be config-
ured with the addition of a CMOS multiplexer (or other switch
network), and a suitable resistor network. Because the ON
resistance of the switches is removed from the signal path, an
AD625 based SPGA will deliver 12-bit precision, and can be
programmed for any set of gains between 1 and 10,000, with
completely user selected gain steps.
For the highest precision the AD625C offers an input offset
voltage drift of less than 0.25 µV/°C, output offset drift below
15 µV/°C, and a maximum nonlinearity of 0.001% at G = 1. All
grades exhibit excellent ac performance; a 25 MHz gain band-
width product, 5 V/µs slew rate and 15 µs settling time.
The AD625 is available in three accuracy grades (A, B, C) for
industrial (–40°C to +85°C) temperature range, two grades (J,
K) for commercial (0°C to +70°C) temperature range, and one
(S) grade rated over the extended (–55°C to +125°C) tempera-
ture range.
PRODUCT HIGHLIGHTS
1. The AD625 affords up to 16-bit precision for user selected
fixed gains from 1 to 10,000. Any gain in this range can be
programmed by 3 external resistors.
2. A 12-bit software programmable gain amplifier can be config-
ured using the AD625, a CMOS multiplexer and a resistor
network. Unlike previous instrumentation amplifier designs,
the ON resistance of a CMOS switch does not affect the gain
accuracy.
3. The gain accuracy and gain temperature coefficient of the
amplifier circuit are primarily dependent on the user selected
external resistors.
4. The AD625 provides totally independent input and output
offset nulling terminals for high precision applications. This
minimizes the effects of offset voltage in gain-ranging
applications.
5. The proprietary design of the AD625 provides input voltage
noise of 4 nV/√Hz at 1 kHz.
6. External resistor matching is not required to maintain high
common-mode rejection.
AD625–SPECIFICATIONS(typical @ VS = �15 V, RL = 2 k� and TA = + 25�C, unless otherwise noted)
AD625
NOTESGain Error and Gain TC are for the AD625 only. Resistor Network errors will add to the specified errors.VDL is the maximum differential input voltage at G = 1 for specified nonlinearity. VDL at other gains = 10 V/G. VD = actual differential input voltage.
Example: G = 10, VD = 0.50; VCM = 12 V – (10/2 × 0.50 V) = 9.5 V.
Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are
used to calculate outgoing quality levels.
AD625
PIN CONNECTIONS
Ceramic DIP (D) and Plastic DIP (N) Packages
Leadless Chip Carrier (E) Package19123
RTI NULL
RTI NULL
+GAIN DRIVE
RTO NULL
RTO NULL
–GAIN NULL
SENSE
+INPUT
REFERENCE
NC
+GAIN SENSE–
GAIN SENSE
OUT
INPUT
ABSOLUTE MAXIMUM RATINGS*
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18V
InternalPowerDissipation . . . . . . . . . . . . . . . . . . . . . .450 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS
DifferentialInputVoltage . . . . . . . . . . . . . . . . . . . . . . . . .±VS
Output Short Circuit Duration . . . . . . . . . . . . . . . .Indefinite
Storage Temperature Range (D, E) . . . . . . . .–65°C to +150°C
Storage Temperature Range (N) . . . . . . . . . .–65°C to +125°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD625 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
*Standard Military Drawing Available
Operating Temperature Range
AD625J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
AD625A/B/C . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
AD625S . . . . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
Lead Temperature Range (Soldering10sec) . . . . . . . .+300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
SUPPLY VOLTAGE – �V
INPUT VOLTAGE RANGE
5101520
Figure 1.Input Voltage Range vs.
Supply Voltage, G = 1
FREQUENCY – Hz
CMRR
dM
–160101001k10k100k10M
–20
Figure 4.CMRR vs. Frequency
RTI, Zero to 1 kΩ Source Imbal-
ance

WARM-UP TIME – Minutes
FROM FINAL VALUE 1.02.03.04.05.06.07.08.0
Figure 7.Offset Voltage, RTI, Turn
On Drift

SUPPLY VOLTAGE – �V
OUTPUT VOLTAGE SWING
5101520
Figure 2.Output Voltage Swing
vs. Supply Voltage
FREQUENCY – Hz
FULL POWER RESPONSE
V p-p10k100k1M
Figure 5.Large Signal Frequency
Response
FREQUENCY – Hz
POWER SUPPLY REJECTION
dB
1001001k10k100k
Figure 8.Negative PSRR vs.
Frequency

LOAD RESISTANCE – �
OUTPUT VOLTAGE SWING
V p-p
1001k10k
Figure 3.Output Voltage Swing
vs. Load Resistance
Figure 6.Gain vs. Frequency

FREQUENCY – Hz
POWER SUPPLY REJECTION
dB
1001001k10k100k
Figure 9.Positive PSRR vs.
Frequency
AD625
TEMPERATURE – �C
INPUT CURRENT
nA
–40–75–252575125
Figure 10.Input Bias Current vs.
Temperature
SUPPLY VOLTAGE – �V
AMPLIFIER QUIESCENT CURRENT
5101520
Figure 13.Quiescent Current vs.
Supply Voltage
Figure 16.Low Frequency Voltage
Noise, G = 1 (System Gain = 1000)
+VS
–VS
AD62510V
Figure 11.Overrange and Gain
Switching Test Circuit (G = 8, G = 1)
Figure 14.RTI Noise Spectral
Density vs. Gain
Figure 17.Noise Test Circuit
Figure 12.Gain Overrange Recovery
Figure 15.Input Current Noise
Figure 18.Low Frequency Voltage
Noise, G = 1000 (System
Gain = 100,000)
Figure 19.Large Signal Pulse
Response and Settling Time, G = 1
Figure 22.Large Signal Pulse
Response and Settling Time, G = 10
Figure 20.Settling Time to 0.01%
Figure 23.Settling Time Test Circuit
Figure 21.Large Signal Pulse
Response and Settling Time, G = 100
Figure 24.Large Signal Pulse
Response and Settling Time,
G = 1000
AD625
THEORY OF OPERATION
The AD625 is a monolithic instrumentation amplifier based on
a modification of the classic three-op-amp approach. Monolithic
construction and laser-wafer-trimming allow the tight matching
and tracking of circuit components. This insures the high level
of performance inherent in this circuit architecture.
A preamp section (Q1–Q4) provides additional gain to A1 and
A2. Feedback from the outputs of A1 and A2 forces the collec-
tor currents of Q1–Q4 to be constant, thereby, impressing the
input voltage across RG. This creates a differential voltage at the
outputs of A1 and A2 which is given by the gain (2RF/RG + 1)
times the differential portion of the input voltage. The unity
gain subtracter, A3, removes any common-mode signal from the
output voltage yielding a single ended output, VOUT, referred to
the potential at the reference pin.
The value of RG is the determining factor of the transconduc-
tance of the input preamp stage. As RG is reduced for larger
gains the transconductance increases. This has three important
advantages. First, this approach allows the circuit to achieve a
very high open-loop gain of (3 × 108 at programmed gains ≥ 500)
thus reducing gain related errors. Second, the gain-bandwidth
product, which is determined by C3, C4, and the input trans-
conductance, increases with gain, thereby, optimizing frequency
response. Third, the input voltage noise is reduced to a value
determined by the collector current of the input transistors
(4 nV/√Hz).
INPUT PROTECTION
Differential input amplifiers frequently encounter input voltages
outside of their linear range of operation. There are two consid-
erations when applying input protection for the AD625; 1) that
continuous input current must be limited to less than 10 mA
and 2) that input voltages must not exceed either supply by
more than one diode drop (approximately 0.6 V @ 25°C).
Under differential overload conditions there is (RG + 100) Ω in
series with two diode drops (approximately 1.2 V) between the
plus and minus inputs, in either direction. With no external protec-
tion and RG very small (i.e., 40 Ω), the maximum overload
voltage the AD625 can withstand, continuously, is approximately2.5 V. Figure 26a shows the external components necessary to
protect the AD625 under all overload conditions at any gain.
The diodes to the supplies are only necessary if input voltages
outside of the range of the supplies are encountered. In higher
gain applications where differential voltages are small, back-to-
back Zener diodes and smaller resistors, as shown in Figure
26b, provides adequate protection. Figure 26c shows low cost
FETs with a maximum ON resistance of 300 Ω configured to offer
input protection with minimal degradation to noise, (5.2 nV/√Hz
compared to normal noise performance of 4 nV/√Hz).
During differential overload conditions, excess current will flow
through the gain sense lines (Pins 2 and 15). This will have no
effect in fixed gain applications. However, if the AD625 is being
used in an SPGA application with a CMOS multiplexer, this
current should be taken into consideration. The current capa-
bilities of the multiplexer may be the limiting factor in allowable
overflow current. The ON resistance of the switch should be
included as part of RG when calculating the necessary input
protection resistance.
AD625
+VS
–VS
–IN
+IN
1.4k�
1.4k�
VOUT
Figure 26a.Input Protection Circuit
AD625
+VS
–VS
–IN
+IN
500�
VOUT
FD333
500�
Figure 26b.Input Protection Circuit for G > 5
AD625
+VS
–VS
–IN
+IN
VOUT
FD333
2N5952
2N5952

Partno	Mfg	Dc	Qty	Available	Descript
AD625AD	AD	N/a	53	avai	Programmable Gain Instrumentation Amplifier
AD625BD	AD	N/a	12	avai	Programmable Gain Instrumentation Amplifier
AD625CD		N/a	32	avai	Programmable Gain Instrumentation Amplifier
AD625JN		N/a	100	avai	Programmable Gain Instrumentation Amplifier
AD625KN	AD	N/a	200	avai	Programmable Gain Instrumentation Amplifier
AD625SD	AD	N/a	300	avai	Programmable Gain Instrumentation Amplifier