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AD621AN-AD621AR-AD621BN-AD621BR
Low Drift, Low Power Instrumentation Amplifier
CONNECTION DIAGRAM
8-Pin Plastic Mini-DIP (N), Cerdip (Q)
and SOIC (R) PackagesREV.A
Low Drift, Low Power
Instrumentation Amplifier
FEATURES
EASY TO USE
Pin-Strappable Gains of 10 & 100
All Errors Specified for Total System Performance
Higher Performance than Discrete In-Amp Designs
Available in 8-Pin DIP and SOIC
Low Power, 1.3 mA max Supply Current
Wide Power Supply Range (62.3 V to 618 V)
EXCELLENT DC PERFORMANCE
0.15% max, Total Gain Error65 ppm/8C, Total Gain Drift
125 mV max, Total Offset Voltage
1.0 mV/8C max, Offset Voltage Drift
LOW NOISE
9 nV/√Hz, @ 1 kHz, Input Voltage Noise
0.28 mV p-p Noise (0.1 Hz to 10 Hz}
EXCELLENT AC SPECIFICATIONS
800 kHz Bandwidth (G = 10}, 200 kHz (G = 100}
12 ms Settling Time to 0.01%
APPLICATIONS
Weigh Scales
Transducer Interface & Data Acquisition Systems
Industrial Process Controls
Battery Powered and Portable Equipment
PRODUCT DESCRIPTIONThe AD621 is an easy to use, low cost, low power, high accu-
racy instrumentation amplifier which is ideally suited for a wide
range of applications. Its unique combination of high perfor-
mance, small size and low power, outperforms discrete in amp
implementations. High functionality, low gain errors and low
gain drift errors are achieved by the use of internal gain setting
resistors. Fixed gains of 10 and 100 can be easily set via external
Three Op Amp IA Designs vs. AD621
pin strapping. The AD621 is fully specified as a total system,
therefore, simplifying the design process.
For portable or remote applications, where power dissipation,
size and weight are critical, the AD621 features a very low sup-
ply current of 1.3 mA max and is packaged in a compact 8-pin
SOIC, 8-pin plastic DIP or 8-pin cerdip. The AD621 also
excels in applications requiring high total accuracy, such as pre-
cision data acquisition systems used in weigh scales and trans-
ducer interface circuits. Low maximum error specifications
including nonlinearity of 10 ppm, gain drift of 5 ppm/°C, 50 μV
offset voltage and 0.6 μV/°C offset drift (“B” grade), make pos-
sible total system performance at a lower cost than has been pre-
viously achieved with discrete designs or with other monolithic
instrumentation amplifiers.
When operating from high source impedances, as in ECG and
blood pressure monitors, the AD621 features the ideal combina-
tion of low noise and low input bias currents. Voltage noise is
specified as 9 nV/√Hz at 1 kHz and 0.28 μV p-p from 0.1 Hz to
10 Hz. Input current noise is also extremely low at 0.1 pA/√Hz.
The AD621 outperforms FET input devices with an input bias
current specification of 1.5 nA max over the full industrial tem-
perature range.
Total Voltage Noise vs. Source Resistance
AD621–SPECIFICATIONS
Gain = 10TOTAL VOLTAGE OFFSET
OUTPUT
DYNAMIC RESPONSE
REFERENCE INPUT
POWER SUPPLY
NOTES
1See Analog Devices military data sheet for 883B tested specifications.This is defined as the supply range over which PSRR is defined.
3Input Voltage Range = CMV + (Gain × VDIFF).
Specifications subject to change without notice.
(typical @ +258C, VS = 615V, and RL = 2 kV, unless otherwise noted)
NOTES
1See Analog Devices military data sheet for 883B tested specifications.This is defined as the supply range over which PSEE is defined.
3Input Voltage Range = CMV + (Gain × VDIFF).
Specifications subject to change without notice.
Gain = 100(typical @ +258C, VS = 615V, and RL = 2 kV, unless otherwise noted)
AD621
AD621NOTESStresses above those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device in free air:
8-Pin Plastic Package: θJA = 95°C/Watt
8-Pin Cerdip Package: θJA = 110°C/Watt
8-Pin SOIC Package: θJA = 155°C/Watt
ABSOLUTE MAXIMUM RATINGS1SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18V
InternalPowerDissipation2 . . . . . . . . . . . . . . . . . . . . .650 mW
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . .±VS
DifferentialInputVoltage . . . . . . . . . . . . . . . . . . . . . . .±25V
Output Short Circuit Duration .. . . . . . . . . . . . . . . .Indefinite
Storage Temperature Range (Q) . . . . . . . . . .–65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . .–65°C to +125°C
Operating Temperature Range
AD621 (A, B) . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
AD621 (S) . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
Lead Temperature Range
(Soldering10seconds) . . . . . . . . . . . . . . . . . . . . . . .+300°C
ESD SUSCEPTIBILITYESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without de-
tection. Although the AD621 features proprietary ESD protec-
tion circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic dis-
charges. Therefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
ORDERING GUIDENOTESN = Plastic DIP; Q = Cerdip; R = SOIC.See Analog Devices' military data sheet for 883B specifications.
METALIZATION PHOTOGRAPHDimensions shown in inches and (mm).
Contact factory for latest dimensions.
Typical Characteristics–AD621Figure 1.Typical Distribution of VOS, Gain = 10
Figure 2.Typical Distribution of VOS, Gain = 100
Figure 3.Typical Distribution of Input Offset Current
Figure 4.Typical Distribution of Input Bias Current
Figure 5.Change in Input Offset Voltage vs. Warm-Up Time
Figure 6.Voltage Noise Spectral Density
AD621Figure 7.Current Noise Spectral Density vs. Frequency
Figure 8a.0.1 Hz to 10 Hz RTI Voltage Noise, Gain = 10
Figure 8b.0.1 Hz to 10 Hz RTI Voltage Noise, G = 100
Figure 9.
Div, 1 Second per Horizontal Div
Figure 11.
Figure 12.Positive PSR vs. Frequency
Figure 13.Negative PSR vs. Frequency
Figure 14.Closed-Loop Gain vs. Frequency
Figure 15.Large Signal Frequency Response
Figure 17.
G = 10
AD621Figure 18.Output Voltage Swing vs. Resistive Load
Figure 19.Large Signal Pulse Response and Settling
Time Gain, G = 10 (0.5 mV = 0.01%), RL = 1 k Ω,
CL = 100 pF
Figure 21.
Time, G = 100 (0.5 mV = 0.1%), RL = 2 kΩ, CL = 100 pF
Figure 22.
RL = 2 kΩ, CL = 100 pF
