AD6122ARS Fast Delivery |IC PHOENIX CO.,LIMITED

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AD6122ARS
CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator
REV. B
CDMA 3 V Transmitter IF Subsystem
with Integrated Voltage Regulator
FUNCTIONAL BLOCK DIAGRAM
I INPUT
Q INPUT
LOCAL
OSCILLATOR
INPUT
COMMON-MODE
REFERENCE
OUTPUT
POWER-
DOWN 11.23 V
REFERENCE
OUTPUT
VPOS
GAIN CONTROL
VOLTAGE
INPUT
GAIN CONTROL
REFERENCE
VOLTAGE
INPUT
TRANSMIT
OUTPUT
POWER-
DOWN 2
VCC
FEATURES
Fully Compliant with IS98A and PCS Specifications
Linear IF Amplifier
–63 dB to +34 dB
Linear-in-dB Gain Control
Temperature-Compensated Gain Control
Quadrature Modulator
Modulates IFs from 50 MHz to 350 MHz
Integral Low Dropout Regulator
Accepts 2.9 V to 4.2 V Input from Battery
Low Power
10.4 mA at Midgain
<10 �A Sleep Mode Operation
Companion Receiver IF Chip Available (AD6121)
APPLICATIONS
CDMA, W-CDMA, AMPS and TACS Operation
QPSK Transmitters
GENERAL DESCRIPTION
The AD6122 is a low power IF transmitter subsystem, specifi-
cally designed for CDMA applications. It consists of an I and Q
modulator, a divide-by-two quadrature generator, high dynamic
range IF amplifiers with voltage-controlled gain and a power-
down control input. An integral low dropout regulator allows
operation from battery voltages from 2.9 V to 4.2 V.
The gain control input accepts an external gain control voltage
input from a DAC. It provides 97 dB of gain control with a
nominal 75 dB/V scale factor. Either an internal or an external
reference may be used to set the gain-control scale factor.
The I and Q modulator accepts differential quadrature base-
band inputs from a CDMA baseband converter. The local oscil-
lator is injected at twice the IF frequency. A divide-by-two
quadrature generator followed by dual polyphase filters ensures
±1° quadrature accuracy.
The modulator provides a common-mode reference output to
bias the transmit DACs in the baseband converter to the same
common-mode voltage as the modulator inputs, allowing dc
coupling between the two ICs and thus eliminating the need to
charge and discharge coupling capacitors. This allows the fastest
power-up and power-down times for the AD6122 and CDMA
baseband ICs.
The AD6122 is fabricated using a 25 GHz ft silicon BiCMOS
process and is packaged in a 28-lead SSOP and a 32-leadless
LPCC chip scale package (5 mm × 5 mm).
AD6122–SPECIFICATIONS(TA = +25�C, VCC = +3.0 V, LO = 2 � IF, REFIN = 1.23 V, LDO Enabled, unless otherwise
noted) NOTE: All powers shown in dBm are referred to 1 k�.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage DVCC, IFVCC, TXVCC to DGND,
IFGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . .600 mW
Operating Temperature Range . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . .+300°C
ORDERING GUIDE
PIN CONFIGURATIONS
LDOC
PD1PD2
NC = NO CONNECT
LDOB
LDOGND
LDOGND
DGND
LOIPP
LOIPN
DVCCMODOPP
QIPP
QIPN
MODCMREF
IIPN
IIPP
IFGND
IFGND
TXOPP
TXOPN
TXVCC
IFGNDIFGND
IFINN
IFINP
MODOPN
IFVCCREFOUT
REFINVGAIN
LDOE
LPCC Package
IFGND
TXVCC
TXOPN
TXOPP
DVCC
LOIPN
LOIPP
PD1
PD2
LDOE
LDOB
DGND
LDOGND
LDOC
IFINN
IFINP
MODOPN
MODOPP
QIPP
QIPN
MODCMREF
VGAIN
REFIN
REFOUT
IFVCC
IIPN
IIPP
IFGND
SSOP Package
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6122 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Thermal Characteristics: 28-lead SSOP Package: θJA = 115.25°C/W.
AD6122
PIN FUNCTION DESCRIPTIONS
Test Figures
Figure 1.Quadrature Modulator’s Characterization Input and Output Impedance Matches
AD6122
Figure 3.General Test Set
10nF
10nF
0.1�F
SPECTRUM
ANALYZER
VREG
453�
205�
453�
0.1�F
VREGOUT
PULL-UP INDUCTORS CHOSEN
FOR PEAK RESPONSE AT THE
TEST FREQUENCY.
10nF
10nF
RF SOURCE
511�
383�
383�
4:1
IFINN
IFINP
1:8
AD6122
Figure 2.IF Amplifier’s Characterization Input and Output Impedance Matches
10nF
10nF
0.1�F
VREG
453�
205�
453�
0.1�F
VREG
PULL-UP INDUCTORS CHOSEN
FOR PEAK RESPONSE AT THE
TEST FREQUENCY.
10nF
10nF
NOISE
SOURCE
TO NOISE
FILTER
METER
4:1
IFINN
IFINP
1:8
AD6122
Figure 4.IF Amplifier’s Noise Figure Test SetResponse Time from PD1 and PD2 Control to IF OutputResponse Time from Gain Control to IF Output
Figure 5.Response Time Setup
AD6122
Figure 6.Spectral Plot at Modulator Outputs: ACPR
Figure 7.Modulator LO Leakage vs. Output Frequency
Figure 8.Modulator Output Desired Sideband vs.
Output Frequency Without Roofing Filter
–Typical Performance Characteristics
Figure 9.Modulator Output Undesired Sideband vs.
Output Frequency
Figure 10.Modulator Gain: Input (dBV) vs. Output (dBm)
OUTPUT FREQUENCY – MHz
THIRD HARMONIC
dBc
–50
Figure 11.Modulator Third Harmonic
Figure 12.IF Amplifier Response Curve: Gain vs.
VGAIN, TA = –40°C, +25°C, +85°C
VGAIN – V
ERROR FROM PREDICTED VALVE
dB
GAIN
dB
–2.0
Figure 13.IF Amplifier Gain and Error vs. VGAIN
Figure 14.IF Amplifier Input IP3 vs. VGAIN
Figure 15.IF Amplifier Input IP3 vs. Supply Voltage
Figure 16.IF Amplifier Input IP3 vs. Frequency
GAIN – dB
NOISE FIGURE
dB
10.0
Figure 17.IF Amplifier Noise Figure vs. Gain
AD6122
FREQUENCY – MHz
GAIN
dB
–40
Figure 18.IF Amplifier Gain vs. Frequency for
VGAIN = 2.5 V, 2.0 V, 1.5 V, 1.0 V
Figure 20.ACPR of Cascaded Modulator, 20 dB Pad and IF
Amplifier: Spectral Plot
VGAIN – V
TOTAL CURRENT CONSUMPTION
mA
10.0
Figure 19.Total Current Consumption vs. VGAIN

Partno	Mfg	Dc	Qty	Available	Descript
AD6122ARS	AD	N/a	10	avai	CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator