AD606JR ,50 MHz, 80 dB Demodulating Logarithmic Amplifier with Limiter OutputSpecifications subject to change without notice.–2– REV. BAD6061ABSOLUTE MAXIMUM RATINGSPIN FUNCTIO ..
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AD606JN-AD606JR
50 MHz, 80 dB Demodulating Logarithmic Amplifier with Limiter Output
REV.B
50 MHz, 80 dB Demodulating
Logarithmic Amplifier with Limiter Output
FEATURES
Logarithmic Amplifier Performance
–75 dBm to +5 dBm Dynamic Range1.5 nV/√Hz Input Noise
Usable to >50 MHz
37.5 mV/dB Voltage Output
On-Chip Low-Pass Output Filter
Limiter Performance61 dB Output Flatness over 80 dB Range
638 Phase Stability at 10.7 MHz over 80 dB Range
Adjustable Output Amplitude
Low Power
+5 V Single Supply Operation
65 mW Typical Power Consumption
CMOS-Compatible Power-Down to 325 mW typ
<5 ms Enable/Disable Time
APPLICATIONS
Ultrasound and Sonar Processing
Phase-Stable Limiting Amplifier to 100 MHz
Received Signal Strength Indicator (RSSI)
Wide Range Signal and Power Measurement
PRODUCT DESCRIPTIONThe AD606 is a complete, monolithic logarithmic amplifier
using a 9-stage “successive-detection” technique. It provides
both logarithmic and limited outputs. The logarithmic output is
from a three-pole post-demodulation low-pass filter and provides
a loadable output voltage of +0.1 V dc to +4 V dc. The logarith-
mic scaling is such that the output is +0.5 V for a sinusoidal
input of –75 dBm and +3.5 V at an input of +5 dBm; over this
range the logarithmic linearity is typically within –0.4 dB. All
scaling parameters are proportional to the supply voltage.
The AD606 can operate above and below these limits, with
reduced linearity, to provide as much as 90 dB of conversion
range. A second low-pass filter automatically nulls the input
offset of the first stage down to the submicrovolt level. Adding
external capacitors to both filters allows operation at input fre-
quencies as low as a few hertz.
The AD606’s limiter output provides a hard-limited signal
output as a differential current of –1.2 mA from open-collector
outputs. In a typical application, both of these outputs are
loaded by 200 W resistors to provide a voltage gain of more than
90 dB from the input. Transition times are 1.5 ns, and the
phase is stable to within –3° at 10.7 MHz for signals from
–75 dBm to +5 dBm.
The logarithmic amplifier operates from a single +5 V supply
and typically consumes 65 mW. It is enabled by a CMOS logic
level voltage input, with a response time of <5 ms. When dis-
abled, the standby power is reduced to <1 mW within 5 ms.
The AD606J is specified for the commercial temperature range
of 0°C to +70°C and is available in 16-lead plastic DIPs or
SOICs. Consult the factory for other packages and temperature
ranges.
FUNCTIONAL BLOCK DIAGRAM
INLOCOMMISUMILOGBFINVLOGOPCMLMLO
LMHILADJFIL2FIL1VPOSPRUPCOMMINHI
AD606–SPECIFICATIONS(@ TA = +258C and supply = +5 V unless otherwise noted; dBm assumes 50 V)POWER-DOWN INTERFACE
Specifications subject to change without notice.
ORDERING GUIDE
PIN DESCRIPTION
Plastic DIP (N)
and
Small Outline (R)
Packages
INLOINHI
COMMCOMM
ISUMPRUP
ILOGVPOS
BFINFIL1
VLOGFIL2
OPCMLADJ
LMLOLMHI
ABSOLUTE MAXIMUM RATINGS1SupplyVoltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . +9V
InternalPowerDissipation2 . . . . . . . . . . . . . . . . . . . 600 mW
Operating Temperature Range . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering60sec) . . . . . . . . +300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device in free air:
16-Lead Plastic DIP Package: qJA = 85°C/W
16-Lead SOIC Package: qJA = 100°C/W
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD606 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
AD606
INPUT LEVEL CONVENTIONSRF logarithmic amplifiers usually have their input specified in
“dBm,” meaning “decibels with respect to 1 mW.” Unfortu-
nately, this is not precise for several reasons.
1. Log amps respond not to power but to voltage. In this re-
spect, it would be less ambiguous to use “dBV” (decibels
referred to 1 V) as the input metric. Also, power is dependent
on the rms (root mean-square) value of the signal, while log
amps are not inherently rms responding.
2. The response of a demodulating log amp depends on the
waveform. Convention assumes that the input is sinusoidal.
However, the AD606 is capable of accurately handling any
input waveform, including ac voltages, pulses and square
waves, Gaussian noise, and so on. See the AD640 data sheet,
which covers the effect of waveform on logarithmic intercept,
for more information.
3. The impedance in which the specified power is measured is
not always stated. In the log amp context it is invariably
assumed to be 50 W. Thus, 0 dBm means “1 mW rms in 50 W,”
and corresponds to an rms voltage of
224 mV.
Popular convention requires the use of dBm to simplify the
comparison of log amp specifications. Unless otherwise stated,
sinusoidal inputs expressed as dBm in 50 W are used to specify
the performance of the AD606 throughout this data sheet. We
will also show the corresponding rms voltages where it helps to
clarify the specification. Noise levels will likewise be given in
dBm; the response to Gaussian noise is 0.5 dB higher than for a
sinusoidal input of the same rms value.
Note that dynamic range, being a simple ratio, is always speci-
fied simply as “dB”, and the slope of the logarithmic transfer
function is correctly specified as “mV/dB,” NOT as “mV/dBm.”
LOGARITHMIC SLOPE AND INTERCEPTA generalized logarithmic amplifier having an input voltage VIN
and output voltage VLOG must satisfy a transfer function of the
form
where, in the case of the AD606, the voltage VIN is the differ-
ence between the voltages on pins INHI and INLO, and the
voltage VLOG is that measured at the output pin VLOG. VY and
VX are fixed voltages that determine the slope and intercept of
the logarithmic amplifier, respectively. These parameters are
inherent in the design of a particular logarithmic amplifier,
although may be adjustable, as in the AD606. When VIN = VX,
the logarithmic argument is one, hence the logarithm is zero. VX
is, therefore, called the logarithmic intercept voltage because the
output voltage VLOG crosses zero for this input. The slope volt-
age VY is can also be interpreted as the “volts per decade” when
using base-10 logarithms as shown here.
Note carefully that VLOG and VLOG in the above paragraph
(and elsewhere in this data sheet) are different. The first is a
voltage; the second is a pin designation.
This equation suggests that the input VIN is a dc quantity, and,
if VX is positive, that VIN must likewise be positive, since the
results in an alternating input voltage being transformed into a
quasi-dc (rectified and filtered) output voltage.
The single supply nature of the AD606 results in common-mode
level of the inputs INHI and INLO being at about +2.5 V (us-
ing the recommended +5 V supply). In normal ac operation,
this bias level is developed internally and the input signal is
coupled in through dc blocking capacitors. Any residual dc
offset voltage in the first stage limits the logarithmic accuracy for
small inputs. In ac operation, this offset is automatically and
continuously nulled via a feedback path from the last stage, pro-
vided that the pins INHI and INLO are not shorted together, as
would be the case if transformer coupling were used for the signal.
While any logarithmic amplifier must eventually conform to the
basic equation shown above, which, with appropriate elabora-
tion, can also fully account for the effect of the signal waveform
on the effective intercept,1 it is more convenient in RF applica-
tions to use a simpler expression. This simplification results
from first, assuming that the input is always sinusoidal, and
second, using a decibel representation for the input level. The
standard representation of RF levels is (incorrectly, in a log amp
context) in terms of power, specifically, decibels above 1 milli-
watt (dBm) with a presumed impedance level of 50 W. That
being the case, we can rewrite the transfer function as
where it must be understood that PIN means the sinusoidal input
power level in a 50 W system, expressed in dBm, and PX is the
intercept, also expressed in dBm. In this case, PIN and PX are
simple, dimensionless numbers. (PX is sometimes called the
“logarithmic offset,” for reasons which are obvious from the
above equation.) VY is still defined as the logarithmic slope,
usually specified as so many millivolts per decibel, or mV/dB.
In the case of the AD606, the slope voltage, VY, is nominally
750 mV when operating at VPOS = 5 V. This can also be ex-
pressed as 37.5 mV/dB or 750 mV/decade; thus, the 80 dB
range equates to 3 V. Figure 1 shows the transfer function of the
AD606. The slope is closely proportional to VPOS, and can more
generally be stated as VY = 0.15 · VPOS. Thus, in those applica-
tions where the scaling must be independent of supply voltage,
this must be stabilized to the required accuracy. In applications
where the output is applied to an A/D converter, the reference
VLOG – Volts DC
INPUT SIGNAL – dBm
+20
3.5–20–40–60
ILOG and OPCM (output common, which is usually grounded).
The nominal slope at this point is 18.75 mV/dB (375 mV/
decade).
In applications where VLOG is taken to an A/D converter which
allows the use of an external reference, this reference input
should also be connected to the same +5 V supply. The power
supply voltage may be in the range +4.5 V to +5.5 V, providing
a range of slopes from nominally 33.75 mV/dB (675 mV/ de-
cade) to 41.25 mV/dB (825 mV/decade).
A buffer amplifier, having a gain of two, provides a final output
scaling at VLOG of 37.5 mV/dB (750 mV/decade). This low-
impedance output can run from close to ground to over +4 V
(using the recommended +5 V supply) and is tolerant of resis-
tive and capacitive loads. Further filtering is provided by a con-
jugate pole pair, formed by internal capacitors which are an
integral part of the output buffer. The corner frequency of the
overall filter is 2 MHz, and the 10%–90% rise time is 150 ns.
Later, we will show how the slope and intercept can be altered
using simple external adjustments. The direct buffer input
BFIN is used in these cases.
The last limiter output is available as complementary currents
from open collectors at pins LMHI and LMLO. These currents
are each 1.2 mA typical with LADJ grounded and may be con-
verted to voltages using external load resistors connected to
VPOS; typically, a 200 W resistor is used on just one output.
The voltage gain is then over 90 dB, resulting in a hard-limited
output for all input levels down to the noise floor. The phasing
is such that the voltage at LMHI goes high when the input
(INHI to INLO) is positive. The overall delay time from the
signal inputs to the limiter outputs is 8 ns. Of particular impor-
tance is the phase stability of these outputs versus input level. At
50 MHz, the phase typically remains within –4° from –70 dBm
to +5 dBm. The rise time of this output (essentially a square
wave) is about 1.2 ns, resulting in clean operation to more than
70 MHz.
for that converter should be a fractional part of VPOS, if possible.
The slope is essentially independent of temperature.
The intercept PX is essentially independent of either the supply
voltage or temperature. However, the AD606 is not factory
calibrated, and both the slope and intercept may need to be
externally adjusted. Following calibration, the conformance to
an ideal logarithmic law will be found to be very close, particu-
larly at moderate frequencies (see Figure 14), and still accept-
able at the upper end of the frequency range (Figure 15).
CIRCUIT DESCRIPTIONFigure 2 is a block diagram of the AD606, which is a complete
logarithmic amplifier system in monolithic form. It uses a total
of nine limiting amplifiers in a “successive detection” scheme to
closely approximate a logarithmic response over a total dynamic
range of 90 dB (Figure 2). The signal input is differential, at
nodes INHI and INLO, and will usually be sinusoidal and ac
coupled. The source may be either differential or single-sided;
the input impedance is about 2.5 kW in parallel with 2 pF. Seven
of the amplifier/detector stages handle inputs from –80 dBm
(32 mV rms) up to about –14 dBm (45 mV rms). The noise floor
is about –83 dBm (18 mV rms). Another two stages receive the
input attenuated by 22.3 dB, and respond to inputs up to
+10 dBm (707 mV rms). The gain of each of these stages is
11.15 dB and is accurately stabilized over temperature by a
precise biasing system.
The detectors provide full-wave rectification of the alternating
signal present at each limiter output. Their outputs are in the
form of currents, proportional to the supply voltage. Each cell
incorporates a low-pass filter pole, as the first step in recovering
the average value of the demodulated signal, which contains
appreciable energy at even harmonics of the input frequency. A
further real pole can be introduced by adding a capacitor be-
tween the summing node ISUM and VPOS. The summed de-
tector output currents are applied to a 6:1 reduction current
mirror. Its output at ILOG is scaled 2 mA/dB, and is converted
to voltage by an internal load resistor of 9.375 kW between
LMHILADJFIL2FIL1VPOSPRUPCOMMINHI
AD606
Offset-Control LoopThe offset-control loop nulls the input offset voltage, and sets
up the bias voltages at the input pins INHI and INLO. A full
understanding of this offset-control loop is useful, particularly
when using larger input coupling capacitors and an external
filter capacitor to lower the minimum acceptable operating
frequency. The loop’s primary purpose is to extend the lower
end of the dynamic range in the case where the offset voltage of
the first stage should be high enough to cause later stages to
prematurely enter limiting, because of the high dc gain (about
8000) of the main amplifier system. For example, an offset
voltage of only 20 mV would become 160 mV at the output of
the last stage in the main amplifier (before the final limiter sec-
tion), driving the last stage well into limiting. In the absence of
noise, this limiting would simply result in the logarithmic output
ceasing to become any lower below a certain signal level at the
input. The offset would also degrade the logarithmic conform-
ance in this region. In practice, the finite noise of the first stage
also plays a role in this regard, even if the dc offset were zero.
Figure 3 shows a representation of this loop, reduced to essen-
tials. The figure closely corresponds to the internal circuitry,
and correctly shows the input resistance. Thus, the forward gain
of the main amplifier section is 7 · 11.15 dB, but the loop gain
is lowered because of the attenuation in the network formed by
RB1 and RB2 and the input resistance RA. The connection
polarity is such as to result in negative feedback, which reduces
the input offset voltage by the dc loop gain, here about 50 dB,
that is, by a factor of about 316. We use a differential representa-
tion, because later we will examine the consequences to the
power-up response time in the event that the ac coupling capaci-
tors CC1 and CC2 do not exactly match. Note that these capaci-
tors, as well as forming a high-pass filter to the signal in the
forward path, also introduce a pole in the feedback path.
Figure 3.Offset Control Loop
Internal resistors RF1 and RF2 in conjunction with grounded
capacitors CF1 and CF2 form a low-pass filter at 15 kHz. This
frequency can optionally be lowered by the addition of an exter-
nal capacitor CZ, and in some cases a series resistor RZ. This, in
conjunction with the low-pass section formed at the input cou-
pling, results in a two-pole high-pass response, falling of at
40 dB/decade below the corner frequency. The damping factor
of this filter depends on the ratio CZ/CC (when CZ>>CF) and
also on the value of RZ.
The loop’s effect is felt only at the lower end of the dynamic
range, that is, from about 80 dBm to –70 dBm, and when the
signal frequency is near the lower edge of the passband. Thus,
the small signal results which are obtained using the suggested
model are not indicative of the ac response at moderate to high
signal levels. Figure 4 shows the response of this model for the
default case (using CC = 100 pF and CZ = 0) and with CZ =
150 pF. In general, a maximally flat ac response occurs when CZ
is roughly twice CC (making due allowance for the internal
30 pF capacitors). Thus, for audio applications, one can use
CC = 2.7 mF and CZ = 4.7 mF to achieve a high-pass corner
(–3 dB) at 25 Hz.
100k100M10M1M10k
INPUT FREQUENCY – Hz
RELATIVE OUTPUT – dBFigure 4.Frequency Response of Offset Control Loop for
CZ = 0 pF and CZ = 150 pF (CC = 100 pF)
However, the maximally flat ac response is not optimal in two
special cases. First, where the RF input level is rapidly pulsed,
the fast edges will cause the loop filter to ring. Second, ringing
can also occur when using the power-up feature, and the ac
coupling capacitors do not exactly match in value. We will ex-
amine the latter case in a moment. Ringing in a linear amplifier
is annoying, but in a log amp, with its much enhanced sensitiv-
ity to near zero signals, it can be very disruptive.
To optimize the low level accuracy, that is, achieve a highly
damped pulse response in this filter, it is recommended to in-
clude a resistor RZ in series with an increased value of CZ. Some
experimentation may be necessary, but for operation in the
range 3 MHz to 70 MHz, values of CC = 100 pF, CZ = 1 nF
and RZ = 2 kW are near optimal. For operation down to 100 kHz
use CC = 10 nF, CZ = 0.1 mF and RZ = 13 kW. Figure 5 shows
typical connections for the AD606 with these filter components
added.
CZ
