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AD603AQ-AD603AR-AD603AR-REEL-AD603AR-REEL7
Low Noise, 90 MHz Variable-Gain Amplifier
REV.C
FEATURES
“Linear in dB” Gain Control
Pin Programmable Gain Ranges
–11 dB to +31 dB with 90 MHz Bandwidth
+9 dB to +51 dB with 9 MHz Bandwidth
Any Intermediate Range, e.g., –1 dB to +41 dB with
30 MHz Bandwidth
Bandwidth Independent of Variable Gain
1.3 nV/√Hz Input Noise Spectral Density60.5 dB Typical Gain Accuracy
MIL-STD-883 Compliant and DESC Versions Available
APPLICATIONS
RF/IF AGC Amplifier
Video Gain Control
A/D Range Extension
Signal Measurement
Low Noise, 90MHz
Variable-Gain Amplifier
PRODUCT DESCRIPTIONThe AD603 is a low noise, voltage-controlled amplifier for use
in RF and IF AGC systems. It provides accurate, pin selectable
gains of –11dB to +31dB with a bandwidth of 90 MHz ordB to +51 dB with a bandwidth of 9 MHz. Any intermediate
gain range may be arranged using one external resistor. The
input referred noise spectral density is only 1.3nV/√Hz and power
consumption is 125 mW at the recommended –5 V supplies.
The decibel gain is “linear in dB,” accurately calibrated, and
stable over temperature and supply. The gain is controlled at a
high impedance (50 MW), low bias (200 nA) differential input;
the scaling is 25 mV/dB, requiring a gain-control voltage of only
FUNCTIONAL BLOCK DIAGRAM
SCALING
REFERENCE
GAIN
CONTROL
INTERFACE
AD603
PRECISION PASSIVE
INPUT ATTENUATOR
FIXED GAIN
AMPLIFIER
*NORMAL VALUESR = 2R LADDER NETWORK
VPOS
VNEG
GPOS
GNEG
VINP
COMM
0dB–6.02dB–12.04dB–18.06dB–24.08dB–30.1dB–36.12dB–42.14dBRRRRR2R2R2R2R2RR
20V*
694V*
6.44kV*
VOUT
FDBK1 V to span the central 40 dB of the gain range. An over- and
under-range of 1 dB is provided whatever the selected range. The
gain-control response time is less than 1ms for a 40 dB change.
The differential gain-control interface allows the use of either
differential or single-ended positive or negative control voltages.
Several of these amplifiers may be cascaded and their gain-con-
trol gains offset to optimize the system S/N ratio.
The AD603 can drive a load impedance as low as 100 W with
low distortion. For a 500 W load in shunt with 5 pF, the total
harmonic distortion for a –1V sinusoidal output at 10 MHz is
typically –60 dBc. The peak specified output is –2.5 V mini-
mum into a 500W load, or –1 V into a 100 W load.
The AD603 uses a proprietary circuit topology—the X-AMP™.
The X-AMP comprises a variable attenuator of 0 dB to
–42.14dB followed by a fixed-gain amplifier. Because of the
attenuator, the amplifier never has to cope with large inputs and
can use negative feedback to define its (fixed) gain and dynamic
performance. The attenuator has an input resistance of 100 W,
laser trimmed to –3%, and comprises a seven-stage R-2R ladder
network, resulting in an attenuation between tap points of
6.021dB. A proprietary interpolation technique provides a
continuous gain-control function which is linear in dB.
The AD603A is specified for operation from –40°C to +85°C
and is available in both 8-lead SOIC (R) and 8-lead ceramic
DIP (Q). The AD603S is specified for operation from –55°C to
+125°C and is available in an 8-lead ceramic DIP (Q). The
AD603 is also available under DESC SMD 5962-94572.
*Patented.X-AMP is a trademark of Analog Devices, Inc.
AD603–SPECIFICATIONSGAIN CONTROL INTERFACE
POWER SUPPLY
NOTESTypical open or short-circuited input; noise is lower when system is set to maximum gain and input is short-circuited. This figure includes the effects of both voltage
and current noise sources.Using resistive loads of 500W or greater, or with the addition of a 1 kW pull-down resistor when driving lower loads.The dc gain of the main amplifier in the AD603 is ·35.7; thus, an input offset of 100 mV becomes a 3.57 mV output offset.GNEG and GPOS, gain control, voltage range is guaranteed to be within the range of –VS + 4.2 V to +VS – 3.4 V over the full temperature range of –40°C to +85°C.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
(@ TA = +258C, VS = 65 V, –500 mV £ VG £ +500 mV, GNEG = 0 V, –10 dB to +30dB Gain
Range, RL = 500V, and CL = 5 pF, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS1SupplyVoltage –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . .–7.5V
InternalVoltage VINP (Pin 3) . . . . . . . . . . . –2 V Continuous
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS for 10 ms
GPOS, GNEG (Pins 1, 2) . . . . . . . . . . . . . . . . . . . . . . . –VS
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 400mW
Operating Temperature Range
AD603A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD603S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering60sec) . . . . . . . .+300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Thermal Characteristics:
8-Lead SOIC Package: qJA = 155°C/W, qJC = 33°C/W
8-Lead Ceramic Package: qJA = 140°C/W, qJC = 15°C/W
PIN FUNCTION DESCRIPTIONS
CONNECTION DIAGRAMS
8-Lead Plastic SOIC (R) Package
8-Lead Ceramic DIP (Q) Package
GPOS
GNEG
VINP
VPOS
VOUT
VNEG
FDBKCOMM
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD603 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*Refer to AD603 Military data sheet. Also available as 5962-9457203MPA.
AD603
THEORY OF OPERATIONThe AD603 comprises a fixed-gain amplifier, preceded by a
broadband passive attenuator of 0dB to 42.14 dB, having a
gain-control scaling factor of 40 dB per volt. The fixed gain is
laser-trimmed in two ranges, to either 31.07 dB (·35.8) ordB (·358), or may be set to any range in between using one
external resistor between Pins 5 and 7. Somewhat higher gain
can be obtained by connecting the resistor from Pin 5 to com-
mon, but the increase in output offset voltage limits the
maximum gain to about 60 dB. For any given range, the band-
width is independent of the voltage-controlled gain. This system
provides an under- and overrange of 1.07 dB in all cases;
for example, the overall gain is –11.07 dB to 31.07 dB in the
maximum-bandwidth mode (Pin 5 and Pin 7 strapped).
This X-AMP structure has many advantages over former methods
of gain-control based on nonlinear elements. Most importantly,
the fixed-gain amplifier can use negative feedback to increase its
accuracy. Since large inputs are first attenuated, the amplifier
input is always small. For example, to deliver a –1 V output in
the –1 dB/+41 dB mode (that is, using a fixed amplifier gain of
41.07 dB) its input is only 8.84 mV; thus the distortion can be
very low. Equally important, the small-signal gain and phase
response, and thus the pulse response, are essentially indepen-
dent of gain.
Figure 1 is a simplified schematic. The input attenuator is a
seven-section R-2R ladder network, using untrimmed resistors
of nominally R = 62.5 W, which results in a characteristic resis-
tance of 125 W – 20%. A shunt resistor is included at the input
and laser trimmed to establish a more exact input resistance of
100 W – 3%, which ensures accurate operation (gain and HP
corner frequency) when used in conjunction with external resistors
or capacitors.
The nominal maximum signal at input VINP is 1 V rms (–1.4 V
peak) when using the recommended –5 V supplies, although
operation to –2 V peak is permissible with some increase in HF
distortion and feedthrough. Pin 4 (SIGNAL COMMON) must
be connected directly to the input ground; significant impedance in
this connection will reduce the gain accuracy.
The signal applied at the input of the ladder network is attenu-
ated by 6.02 dB by each section; thus, the attenuation to each of
the taps is progressively 0 dB, 6.02 dB, 12.04 dB, 18.06 dB,
24.08 dB, 30.1 dB, 36.12 dB and 42.14 dB. A unique circuit
technique is employed to interpolate between these tap-points,
indicated by the “slider” in Figure 1, thus providing continuous
attenuation from 0 dB to 42.14 dB. It will help, in understanding
the AD603, to think in terms of a mechanical means for moving
this slider from left to right; in fact, its “position” is controlled
by the voltage between Pins 1 and 2. The details of the gain-
control interface are discussed later.
The gain is at all times very exactly determined, and a linear-in-
dB relationship is automatically guaranteed by the exponential
nature of the attenuation in the ladder network (the X-AMP
principle). In practice, the gain deviates slightly from the ideal
law, by about –0.2 dB peak (see, for example, Figure 16).
Noise PerformanceAn important advantage of the X-AMP is its superior noise per-
formance. The nominal resistance seen at inner tap points is
41.7 W (one third of 125 W), which exhibits a Johnson noise-
spectral density (NSD) of 0.83 nV/√Hz (that is, √4kTR) at 27°C,
which is a large fraction of the total input noise. The first stage
of the amplifier contributes a further 1nV/√Hz, for a total input
noise of 1.3 nV/√Hz. It will be apparent that it is essential to use
a low resistance in the ladder network to achieve the very low
specified noise level. The signal’s source impedance forms a
voltage divider with the AD603’s 100 W input resistance. In
some applications, the resulting attenuation may be unaccept-
able, requiring the use of an external buffer or preamplifier to
match a high impedance source to the low impedance AD603.
The noise at maximum gain (that is, at the 0 dB tap) depends
on whether the input is short-circuited or open-circuited: when
shorted, the minimum NSD of slightly over 1 nV/√Hz is achieved;
when open, the resistance of 100 W looking into the first tap
generates 1.29 nV/√Hz, so the noise increases to a total of
1.63 nV/√Hz. (This last calculation would be important if the
AD603 were preceded by, for example, a 900 W resistor to allow
operation from inputs up to 10 V rms.) As the selected tap
moves away from the input, the dependence of the noise on
source impedance quickly diminishes.
Apart from the small variations just discussed, the signal-to-
noise (S/N) ratio at the output is essentially independent of the
attenuator setting. For example, on the –11 dB/+31 dB range
the fixed gain of ·35.8 raises the output NSD to 46.5 nV/√Hz.
Thus, for the maximum undistorted output of 1V rms and aMHz bandwidth, the output S/N ratio would be 86.6 dB, that
is, 20 log (1 V/46.5 mV).
SCALING
REFERENCE
GAIN
CONTROL
INTERFACE
AD603
PRECISION PASSIVE
INPUT ATTENUATORFIXED GAIN
AMPLIFIER
VPOS
VNEG
GPOS
GNEG
VINP
0dB–6.02dB–12.04dB–18.06dB–24.08dB–30.1dB–36.12dB–42.14dBRRRRR2R2R2R2R2RR
20V*
694V*
6.44kV*
VOUT
FDBK
The Gain-Control InterfaceThe attenuation is controlled through a differential, high-
impedance (50 MW) input, with a scaling factor which is
laser-trimmed to 40 dB per volt, that is, 25 mV/dB. An internal
bandgap reference ensures stability of the scaling with respect to
supply and temperature variations.
When the differential input voltage VG = 0 V, the attenuator
“slider” is centered, providing an attenuation of 21.07 dB. For
the maximum bandwidth range, this results in an overall gain of
10 dB (= –21.07 dB + 31.07 dB). When the control input is
–500mV, the gain is lowered by 20 dB (= 0.500 V · 40dB/V),
to –10 dB; when set to +500 mV, the gain is increased by 20dB, to
30 dB. When this interface is overdriven in either direction, the
gain approaches either –11.07 dB (= –42.14 dB + 31.07 dB) or
31.07 dB (= 0 + 31.07 dB), respectively. The only constraint on
the gain-control voltage is that it be kept within the common-mode
range (–1.2 V to +2.0 V assuming +5 V supplies) of the gain
control interface.
The basic gain of the AD603 can thus be calculated using the
following simple expression:
Gain (dB) = 40 VG + 10(1)
where VG is in volts. When Pins 5 and 7 are strapped (see next
section) the gain becomes
Gain (dB) = 40 VG + 20 for 0 to +40 dB
and
Gain (dB) = 40 VG + 30 for +10 to +50 dB(2)
The high impedance gain-control input ensures minimal loading
when driving many amplifiers in multiple channel or cascaded
applications. The differential capability provides flexibility in
choosing the appropriate signal levels and polarities for various
control schemes.
For example, if the gain is to be controlled by a DAC providing
a positive only ground-referenced output, the “Gain Control
LO” (GNEG) pin should be biased to a fixed offset of +500mV,
to set the gain to –10 dB when “Gain Control HI” (GPOS) is at
zero, and to 30 dB when at +1.00 V.
It is a simple matter to include a voltage divider to achieve other
scaling factors. When using an 8-bit DAC having an FS output
of +2.55 V (10 mV/bit), a divider ratio of 2 (generating 5 mV/bit)
would result in a gain-setting resolution of 0.2 dB/bit. The use
of such offsets is valuable when two AD603s are cascaded, when
various options exist for optimizing the S/N profile, as will be
shown later.
Programming the Fixed-Gain Amplifier Using Pin StrappingAccess to the feedback network is provided at Pin 5 (FDBK).
The user may program the gain of the AD603’s output amplifier
using this pin, as shown in Figure 2. There are three modes: in
the default mode, FDBK is unconnected, providing the range
+9 dB/+51 dB; when VOUT and FDBK are shorted, the gain is
lowered to –11 dB/+31 dB; when an external resistor is placed
between VOUT and FDBK any intermediate gain can be achieved,
for example, –1 dB/+41 dB. Figure 3 shows the nominal maxi-
mum gain versus external resistor for this mode.
VIN
VOUT–10 dB to +30 dB; 90 MHz Bandwidth
VIN
VOUT0 dB to +40 dB; 30 MHz Bandwidth
VIN
VOUT+10 dB to +50 dB; 9 MHz Bandwidth
Figure 2.Pin Strapping to Set Gain
REXT1M
DECIBELS
1001k10k100kFigure 3.Gain vs. REXT, Showing Worst-Case Limits
Assuming Internal Resistors Have a Maximum Tolerance
of 20%
AD603Optionally, when a resistor is placed from FDBK to COMM,
higher gains can be achieved. This fourth mode is of limited
value because of the low bandwidth and the elevated output off-
sets; it is thus not included in Figure 2.
The gain of this amplifier in the first two modes is set by the
ratio of on-chip laser-trimmed resistors. While the ratio of these
resistors is very accurate, the absolute value of these resistors
can vary by as much as –20%. Thus, when an external resistor
is connected in parallel with the nominal 6.44 kW – 20% inter-
nal resistor, the overall gain accuracy is somewhat poorer. The
worst-case error occurs at about 2 kW (see Figure 4).
REXT
1.21M
DECIBELS
1001k10k100k
–1.0Figure 4.Worst-Case Gain Error, Assuming Internal Resis-
tors Have a Maximum Tolerance of –20% (Top Curve) or
+20% (Bottom Curve)
While the gain-bandwidth product of the fixed-gain amplifier is
about 4 GHz, the actual bandwidth is not exactly related to the
maximum gain. This is because there is a slight enhancing of the
ac response magnitude on the maximum bandwidth range, due
to higher order poles in the open-loop gain function; this mild
peaking is not present on the higher gain ranges. Figure 2 shows
how optional capacitors may be added to extend the frequency
response in high gain modes.
CASCADING TWO AD603STwo or more AD603s can be connected in series to achieve
higher gain. Invariably, ac coupling must be used to prevent the
dc offset voltage at the output of each amplifier from overload-
ing the following amplifier at maximum gain. The required high
pass coupling network will usually be just a capacitor, chosen to
set the desired corner frequency in conjunction with the well-
defined 100 W input resistance of the following amplifier.
For two AD603s, the total gain-control range becomes 84 dB
(two times 42.14 dB); the overall –3 dB bandwidth of cascaded
stages will be somewhat reduced. Depending on the pin-strapping,
the gain and bandwidth for two cascaded amplifiers can range
from –22 dB to +62 dB (with a bandwidth of about 70 MHz) to
+22 dB to +102 dB (with a bandwidth of about 6 MHz).
There are several ways of connecting the gain-control inputs in
cascaded operation. The choice depends on whether it is impor-
tant to achieve the highest possible Instantaneous Signal-to-Noise
Ratio (ISNR), or, alternatively, to minimize the ripple in the gain
error. The following examples feature the AD603 programmed
for maximum bandwidth; the explanations apply to other gain/
bandwidth combinations with appropriate changes to the arrange-
ments for setting the maximum gain.
Sequential Mode (Optimal S/N Ratio)In the sequential mode of operation, the ISNR is maintained at
its highest level for as much of the gain control range possible.
Figure 5 shows the SNR over a gain range of –22 dB to +62 dB,
assuming an output of 1 V rms and a 1 MHz bandwidth; Figure
6 shows the general connections to accomplish this. Here, both
the positive gain-control inputs (GPOS) are driven in parallel by
a positive-only, ground-referenced source with a range of 0 V to
+2 V, while the negative gain-control inputs (GNEG) arc biased
by stable voltages to provide the needed gain-offsets. These volt-
ages may be provided by resistive dividers operating from a
common voltage reference.
S/N RATIO – dB
–0.22.20.20.61.01.41.8Figure 5.SNR vs. Control Voltage—Sequential Control
(1 MHz Bandwidth)
The gains are offset (Figure 7) such that A2’s gain is increased
only after A1’s gain has reached its maximum value. Note that
for a differential input of –600 mV or less, the gain of a single
amplifier (A1 or A2) will be at its minimum value of –11.07 dB;
for a differential input of +600 mV or more, the gain will be at
its maximum value of 31.07 dB. Control inputs beyond these
limits will not affect the gain and can be tolerated without dam-
age or foldover in the response. This is an important aspect of
the AD603’s gain-control response. (See the Specifications sec-
tion of this data sheet for more details on the allowable voltage
range) The gain is now
Gain (dB) = 40VG + GO(3)
where VG is the applied control voltage and GO is determined
by the gain range chosen. In the explanatory notes that follow,
we assume the maximum-bandwidth connections are used, for
which GO is –20 dB.
–40.00dB–51.07dBINPUT
0dB
VC = 0V
OUTPUT
–20dB
0dB–11.07dBINPUT
0dB
VC = 1.0V
OUTPUT
20dB
0dB–28.93dBINPUT
0dB
VC = 2.0V
OUTPUT
60dBFigure 6.AD603 Gain Control Input Calculations for Sequential Control Operation
+31.07dB
+10dBA1A2
+31.07dB+28.96dB
–11.07dB
–11.07dB
–8.93dB0.51.01.502.0VC (V)
GAIN
(dB)
*GAIN OFFSET OF 1.07dB, OR 26.75mVFigure 7.Explanation of Offset Calibration for Sequential
Control
With reference to Figure 6, note that VG1 refers to the differen-
tial gain-control input to A1 and VG2 refers to the differential
gain-control input to A2. When VG is zero, VG1 = –473 mV and
thus the gain of A1 is –8.93 dB (recall that the gain of each indi-
vidual amplifier in the maximum-bandwidth mode is –10 dB
for VG = –500 mV and 10 dB for VG = 0 V); meanwhile, VG2 =
–1.908 V so the gain of A2 is “pinned” at –11.07 dB. The over-
all gain is thus –20 dB. This situation is shown in Figure 6a.
When VG = +1.00 V, VG1 = 1.00 V – 0.473 V = +0.526 V,
which sets the gain of A1 to at nearly its maximum value of
31.07 dB, while VG2 = 1.00 V – 1.526 V = 0.526 V, which sets
A2’s gain at nearly its minimum value –11.07 dB. Close analysis
shows that the degree to which neither AD603 is completely
pushed to its maximum or minimum gain exactly cancels in the
overall gain, which is now +20 dB. This is depicted in Figure 6b.
When VG = +2.0 V, the gain of A1 is pinned at 31.07 dB and
that of A2 is near its maximum value of 28.93 dB, resulting in
an overall gain of 60 dB (see Figure 6c). This mode of operation
is further clarified by Figure 8, which is a plot of the separate
gains of A1 and A2 and the overall gain versus the control voltage.
Figure 9 is a plot of the gain error of the cascaded amplifiers versus
the control voltage. Figure 10 is a plot of the gain error of the
cascaded stages versus the control voltages.
OVERALL GAIN – dB
–20Figure 8. Plot of Separate and Overall Gains in Sequential
Control
