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AD598AD-AD598JR
LVDT Signal Conditioner
PRODUCT DESCRIPTIONThe AD598 is a complete, monolithic Linear Variable Differen-
tial Transformer (LVDT) signal conditioning subsystem. It is
used in conjunction with LVDTs to convert transducer mechan-
ical position to a unipolar or bipolar dc voltage with a high
degree of accuracy and repeatability. All circuit functions are
included on the chip. With the addition of a few external passive
components to set frequency and gain, the AD598 converts the
raw LVDT secondary output to a scaled dc signal. The device
can also be used with RVDT transducers.
The AD598 contains a low distortion sine wave oscillator to
drive the LVDT primary. The LVDT secondary output consists
of two sine waves that drive the AD598 directly. The AD598
operates upon the two signals, dividing their difference by their
sum, producing a scaled unipolar or bipolar dc output.
The AD598 uses a unique ratiometric architecture (patent pend-
ing) to eliminate several of the disadvantages associated with
traditional approaches to LVDT interfacing. The benefits of this
new circuit are: no adjustments are necessary, transformer null
voltage and primary to secondary phase shift does not affect sys-
tem accuracy, temperature stability is improved, and transducer
interchangeability is improved.
The AD598 is available in two performance grades:
It is also available processed to MIL-STD-883B, for the military
range of –55°C to +125°C.
FUNCTIONAL BLOCK DIAGRAMREV.A
LVDT Signal
Conditioner
PRODUCT HIGHLIGHTSThe AD598 offers a monolithic solution to LVDT and
RVDT signal conditioning problems; few extra passive com-
ponents are required to complete the conversion from me-
chanical position to dc voltage and no adjustments are
required.The AD598 can be used with many different types of
LVDTs because the circuit accommodates a wide range of
input and output voltages and frequencies; the AD598 can
drive an LVDT primary with up to 24 V rms and accept sec-
ondary input levels as low as 100 mV rms.The 20 Hz to 20 kHz LVDT excitation frequency is deter-
mined by a single external capacitor. The AD598 input sig-
nal need not be synchronous with the LVDT primary drive.
This means that an external primary excitation, such as the
400 Hz power mains in aircraft, can be used.The AD598 uses a ratiometric decoding scheme such that
primary to secondary phase shifts and transducer null voltage
have absolutely no effect on overall circuit performance.Multiple LVDTs can be driven by a single AD598, either in
series or parallel as long as power dissipation limits are not
exceeded. The excitation output is thermally protected.The AD598 may be used in telemetry applications or in hos-
tile environments where the interface electronics may be re-
mote from the LVDT. The AD598 can drive an LVDT at
the end of 300 feet of cable, since the circuit is not affected
by phase shifts or absolute signal magnitudes. The position
output can drive as much as 1000 feet of cable.The AD598 may be used as a loop integrator in the design of
simple electromechanical servo loops.
FEATURES
Single Chip Solution, Contains Internal Oscillator and
Voltage Reference
No Adjustments Required
Insensitive to Transducer Null Voltage
Insensitive to Primary to Secondary Phase Shifts
DC Output Proportional to Position
20 Hz to 20 kHz Frequency Range
Single or Dual Supply Operation
Unipolar or Bipolar Output
Will Operate a Remote LVDT at Up to 300 Feet
Position Output Can Drive Up to 1000 Feet of Cable
Will Also Interface to an RVDT
Outstanding Performance
Linearity: 0.05% of FS max
Output Voltage: 611 V min
Gain Drift: 50 ppm/8C of FS max
Offset Drift: 50 ppm/8C of FS max
AD598–SPECIFICATIONS
(typical @ +258C and 615 V dc, C1 = 0.015 mF, R2 = 80 kV, RL = 2 kV,
unless otherwise noted. See Figure 7.)SIGNAL INPUT CHARACTERISTICS
POWER SUPPLY REQUIREMENTS
NOTESVA and VB represent the Mean Average Deviation (MAD) of the detected sine waves. Note that for this Transfer Function to linearly represent positive displacement,
the sum of VA and VB of the LVDT must remain constant with stroke length. See “Theory of Operation.” Also see Figures 7 and 12 for R2.From TMIN, to TMAX, the overall error due to the AD598 alone is determined by combining gain error, gain drift and offset drift. For example the worst case overall
error for the AD598AD from TMIN to TMAX is calculated as follows: overall error = gain error at +25°C (±1% full scale) + gain drift from –40°C to +25°C (50 ppm/°C
of FS × +65°C) + offset drift from –40°C to +25°C (50 ppm/°C of FS × +65°C) = ±1.65% of full scale. Note that 1000 ppm of full scale equals 0.1% of full scale.
Full scale is defined as the voltage difference between the maximum positive and maximum negative output.Nonlinearity of the AD598 only, in units of ppm of full scale. Nonlinearity is defined as the maximum measured deviation of the AD598 output voltage from a
straight line. The straight line is determined by connecting the maximum produced full-scale negative voltage with the maximum produced full-scale positive voltage.See Transfer Function.This offset refers to the (VA–VB)/(VA+VB) input spanning a full-scale range of ±1. [For (VA–VB)/(VA+VB) to equal +1, VB must equal zero volts; and correspondingly
for (VA–VB)/(VA+VB) to equal –1, VA must equal zero volts. Note that offset errors do not allow accurate use of zero magnitude inputs, practical inputs are limited to
100 mV rms.] The ±1 span is a convenient reference point to define offset referred to input. For example, with this input span a value of R2 = 20 kΩ would give
VOUT span a value of ±10 volts. Caution, most LVDTs will typically exercise less of the ((VA–VB))/((VA+VB)) input span and thus require a larger value of R2 to
produce the ±10 V output span. In this case the offset is correspondingly magnified when referred to the output voltage. For example, a Schaevitz E100 LVDT
requires 80.2 kΩ for R2 to produce a ±10.69 V output and (VA–VB)/(VA+VB) equals 0.27. This ratio may be determined from the graph shown in Figure 18,
(VA–VB)/(VA+VB) = (1.71 V rms – 0.99 V rms)/(1.71 V rms + 0.99 V rms). The maximum offset value referred to the ±10.69 V output may be determined by
multiplying the maximum value shown in the data sheet (±1% of FS by 1/0.27 which equals ±3.7% maximum. Similarly, to determine the maximum values of offset
drift, offset CMRR and offset PSRR when referred to the ±10.69 V output, these data sheet values should also be multiplied by (1/0.27). For this example for the
AD598AD the maximum values of offset drift, PSRR offset and CMRR offset would be: 185 ppm/°C of FS; 741 ppm/V and 741 ppm/V respectively when referred
to the ±10.69 V output.For example, if the excitation to the primary changes by 1 dB, the gain of the system will change by typically 100 ppm.Output ripple is a function of the AD598 bandwidth determined by C2, C3 and C4. See Figures 16 and 17.R1 is shown in Figures 7 and 12.Excitation voltage drift is not an important specification because of the ratiometric operation of the AD598.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tested are used to calculate outgoing quality levels. All
min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
AD598
THERMAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGSTotal SupplyVoltage +VS to –VS . . . . . . . . . . . . . . . . .+36V
Storage Temperature Range
R Package . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
D Package . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Operating Temperature Range
AD598JR . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
AD598AD . . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Lead Temperature Range (Soldering60sec) . . . . . . . .+300°C
Power Dissipation Up to +65°C . . . . . . . . . . . . . . . . . . .1.2 W
Derates Above +65°C . . . . . . . . . . . . . . . . . . . . . . .12 mW/°C
ORDERING GUIDE
AD598–Typical Characteristics(at +258C and VS = 615 V, unless otherwise noted)
THEORY OF OPERATIONA block diagram of the AD598 along with an LVDT (Linear
Variable Differential Transformer) connected to its input is
shown in Figure 5. The LVDT is an electromechanical trans-
ducer whose input is the mechanical displacement of a core and
whose output is a pair of ac voltages proportional to core posi-
tion. The transducer consists of a primary winding energized by
an external sine wave reference source, two secondary windings
connected in series, and the moveable core to couple flux be-
tween the primary and secondary windings.
The AD598 energizes the LVDT primary, senses the LVDT
secondary output voltages and produces a dc output voltage
proportional to core position. The AD598 consists of a sine
wave oscillator and power amplifier to drive the primary, a de-
coder which determines the ratio of the difference between the
LVDT secondary voltages divided by their sum, a filter and an
output amplifier.
The oscillator comprises a multivibrator which produces a
triwave output. The triwave drives a sine shaper, which pro-
duces a low distortion sine wave whose frequency is determined
by a single capacitor. Output frequency can range from 20 Hz to
20 kHz and amplitude from 2 V rms to 24 V rms. Total har-
monic distortion is typically –50 dB.
Figure 1.Gain and Offset PSRR vs. Temperature
Figure 3.Gain and Offset CMRR vs. Temperature
TEMPERATURE – °C
TYPICAL GAIN DRIFT – ppm/Figure 2.Typical Gain Drift vs. Temperature
a voltage proportional to position. This technique uses the pri-
mary excitation voltage as a phase reference to determine the
polarity of the output voltage. There are a number of problems
associated with this technique such as (1) producing a constant
amplitude, constant frequency excitation signal, (2) compensating
for LVDT primary to secondary phase shifts, and (3) compen-
sating for these shifts as a function of temperature and frequency.
The AD598 eliminates all of these problems. The AD598 does
not require a constant amplitude because it works on the ratio of
the difference and sum of the LVDT output signals. A constant
frequency signal is not necessary because the inputs are rectified
and only the sine wave carrier magnitude is processed. There is
no sensitivity to phase shift between the primary excitation and
the LVDT outputs because synchronous detection is not em-
ployed. The ratiometric principle upon which the AD598 oper-
ates requires that the sum of the LVDT secondary voltages
remains constant with LVDT stroke length. Although LVDT
manufacturers generally do not specify the relationship between
VA+VB and stroke length, it is recognized that some LVDTs do
not meet this requirement. In these cases a nonlinearity will
result. However, the majority of available LVDTs do in fact
meet these requirements.
The AD598 utilizes a special decoder circuit. Referring to the
block diagram and Figure 6 below, an implicit analog comput-
ing loop is employed. After rectification, the A and B signals are
multiplied by complementary duty cycle signals, d and (I–d)
respectively. The difference of these processed signals is inte-
grated and sampled by a comparator. It is the output of this
comparator that defines the original duty cycle, d, which is fed
back to the multipliers.
As shown in Figure 6, the input to the integrator is [(A+B)d]B.
Since the integrator input is forced to 0, the duty cycle d =
B/(A+B).
The output comparator which produces d = B/(A+B) also con-
trols an output amplifier driven by a reference current. Duty
cycle signals d and (1–d) perform separate modulations on the
reference current as shown in Figure 6, which are summed. The
summed current, which is the output current, is IREF × (1–2d).
Since d = B/(A+B), by substitution the output current equals
IREF × (A–B)/(A+B). This output current is then filtered and
converted to a voltage since it is forced to flow through the scal-
ing resistor R2 such that: VOUT=IREF×(A±B)/(A+B)×R2
CONNECTING THE AD598The AD598 can easily be connected for dual or single supply
operation as shown in Figures 7 and 12. The following general
design procedures demonstrate how external component values
are selected and can be used for any LVDT which meets AD598
input/output criteria.
Parameters which are set with external passive components in-
clude: excitation frequency and amplitude, AD598 system
bandwidth, and the scale factor (V/inch). Additionally, there are
optional features, offset null adjustment, filtering, and signal in-
tegration which can be used by adding external components.
AD598
DESIGN PROCEDURE
DUAL SUPPLY OPERATIONFigure 7 shows the connection method with dual ±15 volt power
supplies and a Schaevitz E100 LVDT. This design procedure
can be used to select component values for other LVDTs as
well. The procedure is outlined in Steps 1 through 10 as follows:Determine the mechanical bandwidth required for LVDT
position measurement subsystem, fSUBSYSTEM. For this
example, assume fSUBSYSTEM = 250 Hz.Select minimum LVDT excitation frequency, approximately
10 × fSUBSYSTEM. Therefore, let excitation frequency = 2.5 kHz.Select a suitable LVDT that will operate with an excitation
frequency of 2.5 kHz. The Schaevitz E100, for instance, will
operate over a range of 50 Hz to 10 kHz and is an eligible
candidate for this example.Determine the sum of LVDT secondary voltages VA and VB.
Energize the LVDT at its typical drive level VPRI as shown in
the manufacturer’s data sheet (3 V rms for the E100). Set the
core displacement to its center position where VA = VB. Mea-
sure these values and compute their sum VA+VB. For the
E100, VA+VB = 2.70 V rms. This calculation will be used
later in determining AD598 output voltage.Determine optimum LVDT excitation voltage, VEXC. With
the LVDT energized at its typical drive level VPRI, set the
core displacement to its mechanical full-scale position and
measure the output VSEC of whichever secondary produces
the largest signal. Compute LVDT voltage transformation
ratio, VTR.
VTR = VPRI/VSEC
For the E100, VSEC = 1.71 V rms for VPRI = 3 V rms.
VTR = 1.75.
The AD598 signal input, VSEC, should be in the range of
1 V rms to 3.5 V rms for maximum AD598 linearity and
minimum noise susceptibility. Select VSEC = 3 V rms. There-
fore, LVDT excitation voltage VEXC should be:
VEXC = VSEC × VTR = 3 × 1.75 = 5.25 V rms
Check the power supply voltages by verifying that the peak
values of VA and VB are at least 2.5 volts less than the volt-
ages at +VS and –VS.Referring to Figure 7, for VS = ±15 V, select the value of the
amplitude determining component R1 as shown by the curve
in Figure 8.Select excitation frequency determining component C1.
C1 = 35 μF Hz/fEXCITATION
Figure 8.Excitation Voltage VEXC vs. R1
C2, C3 and C4 are a function of the desired bandwidth ofthe AD598 position measurement subsystem. They should
be nominally equal values.
C2 = C3 = C4 = 10–4 Farad Hz/fSUBSYSTEM (Hz)
If the desired system bandwidth is 250 Hz, then
C2 = C3 = C4 = 10–4 Farad Hz/250 Hz = 0.4 μF
See Figures 13, 14 and 15 for more information about
AD598 bandwidth and phase characterization.In order to Compute R2, which sets the AD598 gain or full-
scale output range, several pieces of information are needed:
a. LVDT sensitivity, S
b.Full-scale core displacement, dRatio of manufacturer recommended primary drive level,
VPRI to (VA + VB) computed in Step 4.
LVDT sensitivity is listed in the LVDT manufacturer’s cata-
log and has units of millivolts output per volts input per inch
displacement. The E100 has a sensitivity of 2.4 mV/V/mil.
In the event that LVDT sensitivity is not given by the manu-
facturer, it can be computed. See section on Determining
LVDT Sensitivity.
For a full-scale displacement of d inches, voltage out of the
AD598 is computed as
VOUT=S×VPRI
(VA+VB)×500μA×R2×d.
VOUT is measured with respect to the signal reference,
Pin 17 shown in Figure 7.
Solving for R2, =VOUT×(VA+VB)×VPRI×500μA×d(1)
Note that VPRI is the same signal level used in Step 4 to
determine (VA + VB).
For VOUT = 20 V full-scale range (±10 V) and d = 0.2 inch
full-scale displacement (±0.1 inch), =20V×2.70V
2.4×3×500μA×0.2=75.3kΩ
VOUT as a function of displacement for the above example is
shown in Figure 9.
d–OUT(VOLTS)
(INCHES)Figure 9. VOUT (±10 V Full Scale)
vs. Core Displacement (±0.1 Inch)
10.Selections of R3 and R4 permit a positive or negative output
voltage offset adjustment.
For no offset adjustment R3 and R4 should be open circuit.
To design a circuit producing a 0 V to +10 V output for a
displacement of ±0.1 inch, set VOUT to +10 V, d = 0.2 inch
and solve Equation (1) for R2.
R2 = 37.6 kΩ
This will produce a response shown in Figure 10.
Figure 10. VOUT (±5 V Full Scale)
vs. Core Displacement (±0.1 Inch)
In Equation (2) set VOS = 5 V and solve for R3 and R4.
Since a positive offset is desired, let R4 be open circuit.
Rearranging Equation (2) and solving for R3
Figure 11 shows the desired response.
Figure 11. VOUT (0 V–10 V Full Scale)
vs. Displacement (±0.1 Inch)
DESIGN PROCEDURE
SINGLE SUPPLY OPERATIONFigure 12 shows the single supply connection method.
For single supply operation, repeat Steps 1 through 10 of the
design procedure for dual supply operation, then complete the
additional Steps 11 through 14 below. R5, R6 and C5 are addi-
tional component values to be determined. VOUT is measured
with respect to SIGNAL REFERENCE.
11.Compute a maximum value of R5 and R6 based upon the
relationship
12.The voltage drop across R5 must be greater than
2+10kΩ*
Therefore
R5≥
2+10kΩ*
