AD5934YRSZ ,250 kSPS 12-Bit Impedance Converter Network AnalyzerSPECIFICATIONS VDD = +3.0 V ± 10%. TMIN to TMAX unless otherwise noted. Table 1. 1 B Version Para ..
AD594AD ,Monolithic Thermocouple Amplifiers with Cold Junction CompensationSpecifications shown in boldface are tested on all production units at final electrical test. Resul ..
AD594AQ ,Monolithic Thermocouple Amplifiers with Cold Junction Compensationapplications.to produce a high level (10 mV/
AD5934YRSZ
250 kSPS 12-Bit Impedance Converter Network Analyzer
250KSPS 12 Bit Impedance Converter
Network Analyzer
Rev. PrA
FEATURES
50KHz Max Excitation Output
Impedance Range .1k – 20M Ohm, 12-Bit Resolution
System Clock provided via MCLK pin
DSP Real and Imaginary Calculation (FFT)
3V Power Supply, Programmable Sinewave Output
Frequency Resolution 27 Bits (<0.1 Hz)
Frequency Sweep Capability
12-Bit Sampling ADC
ADC Sampling 250KSPS, INL ± 1LSB Max
Serial I2C Loading
Temperature Range −40 – 125°C
16 SSOP
APPLICATIONS
Complex Impedance Measurement
Impedance Spectrometry
Biomedical and Automotive Sensors
Proximity Sensors
FFT Processing
GENERAL DESCRIPTION The AD5934 is a high precision impedance converter system
solution which combines an on-board frequency generator with
a 12-bit 250KSPS ADC. The frequency generator allows an
external complex impedance to be excited with a known
frequency. The response signal from the impedance is sampled
by the onboard ADC and FFT processed by an onboard DSP
engine. The FFT algorithm returns a Real (R) and Imaginary (I)
data word, allowing impedance to be conveniently calculated.
The impedance magnitude and phase is easily calculated using
the following equations: Magnitude= )RTanPhase1−=
To determine the actual real impedance value Z(W), a
frequency sweep is generally performed. The impedance can be
calculated at each point, and a frequency vs. magnitude plot can
be created.
The system allows the user to program a 2 V PK-PK sinusoidal
signal as excitation to an external load. Output ranges of 1 V,
500 mV, and 200 mV can also be programmed. The signal is
provided on chips using DDS techniques. Frequency resolution
of 27 bits (less than 0.1HZ) can be achieved.
To perform the frequency sweep, the user must first program
the conditions required for the sweep; start frequency, delta
frequency, step frequency, etc. A Start Command is then
required to begin the sweep.
At each point on the sweep the, ADC takes 1024 samples and
calculates a Discrete Fourier Transform to provide the real and
imaginary data for the waveform. The real and imaginary data
is available to the user through the 12C interface.
To determine the impedance of the load at any one frequency
point, Z(w), a measurement system comprised of a trans
impedance amplifier, gain stage, and ADC are used to record
data. The gain stage for the response stage is 1 or 5.
The ADC is a low-noise, high-speed 250 KSPS sampling ADC
that operates from a 3 V supply. Clocking for both the DDS and
ADC signals is provided externally via the MCLK reference
clock, which is provided externally from a crystal oscillator. The
AD5934 is available in a 16 ld SSOP.
Figure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Characteristics.....................................................................5
Pin Configuration and Function Descriptions.............................6
General Description.........................................................................7
Output Stage..................................................................................7
Circuit Description.......................................................................7
Sin Rom..........................................................................................8
Response Stage..............................................................................8
ADC Operation............................................................................8
DFT Conversion...........................................................................9
Register Map....................................................................................10
Control Register..........................................................................11
Control Register Map.................................................................11
Control Register Decode...........................................................12
Reset.............................................................................................12
System Clock...............................................................................12
Output Voltage............................................................................12
Post Gain.....................................................................................12
Serial Bus Interface.....................................................................13
General I2C Timing...................................................................13
Writing/Reading to the AD5934..........................................14
Write Byte/Command Byte.......................................................14
Block Write..................................................................................15
Read Operations.........................................................................15
P.E.C.............................................................................................16
Checksum....................................................................................16
Outline Dimensions.......................................................................17
ESD Caution................................................................................17
REVISION HISTORY 12/04—Revision PrA – Preliminary Version
SPECIFICATIONS VDD = +3.0 V ± 10%. TMIN to TMAX unless otherwise noted.
Table 1.
Temperature ranges are as follows: B Version: −40°C to +125°C, typical at 25°C.
2 Guaranteed by design and characterization, not production tested.
TIMING CHARACTERISTICS
Table 2. I2C Serial Interface Figure 2. I2C Interface Timing Diagram
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration
Table 3. Pin Function Descriptions GENERAL DESCRIPTION The AD5934 is a high precision impedance converter system
solution which combines an onboard frequency generator with
a 12-bit 1MSPS ADC. The frequency generator allows an
external complex impedance to be excited with a known
frequency. The response signal from the impedance is sampled
by the on board ADC and FFT processed by an onboard DSP
engine. The FFT algorithm returns two Real (R) and Imaginary
(I) data words. The impedance magnitude and phase is easily
calculated using the following equations: Magnitude= RITanPhase1−=
To determine the actual real impedance value Z(W), a
frequency sweep is generally performed. The impedance can be
calculated at each point, and a frequency vs. magnitude plot can
be created.
Figure 4.
The system allows the user to program a 2V PK-PK sinusoidal
signal as excitation to an external load. Output ranges of 1V,
500mV, 200mV can also be programmed. The signal is provided
on chip using DDS techniques. Frequency resolution of 27 bits
(less than 0.1HZ) can be achieved. The clock for the DDS can
be generated from an external reference clock, an internal RC
oscillator, or an internal PLL. The PLL has a gain stage of 520,
and typically needs a reference clock of 32 KHz on the MCLK
pin.
OUTPUT STAGE The output stage of the AD5934, shown in Figure 5, provides a
constant output frequency or frequency sweep function which
has a programmable output voltage of 2/1/0.5/0.2 V. The
frequency sweep sequence is pre-programmed through the I2C
interface. An I2C command is used to start the excitation
sequence.
Figure 5.
CIRCUIT DESCRIPTION The AD5934 has a fully integrated Direct Digital Synthesis
(DDS) core to generate required frequencies. The block requires
a reference clock to provide digitally created sine waves up to
50KHz. This is provided through an external reference clock,
MCLK. This clock is internally divided down by 4 to provide
the reference clock or fMCLK to the DDS. The internal circuitry of
the DDS consists of the following main sections: a Numerical
Controlled Oscillator (NCO), a Frequency Modulator, SIN
ROM, and a digital-to-analog converter.
Numerical Controlled Oscillator and Phase Modulator The main component of the NCO is a 27-bit phase accumulator,
which assembles the phase component of the output signal.
Figure 6.
Continuous time signals have a phase range of 0 to 2 pi. Outside
this range of numbers, the sinusoid functions repeat themselves
in a periodic manner. The digital implementation is no
different. The accumulator simply scales the range of phase
numbers into a multi-bit digital word. The phase accumulator
in the DDS is implemented with 28 bits. Therefore, 2p = 227.
Likewise, the DPhase term is scaled into this range of numbers
0 < DPhase < 227 − 1. Making these substitutions into the
equation above 2MCLKfDPhasef×=
where 0 < DPhase < 227 − 1.
(Note. fmclk = MCLK/4)
The input to the phase accumulator (i.e., the phase step) is
selected from the frequency register. NCOs inherently generate
continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies.
SIN ROM To make the output from the NCO useful, it must be converted
from phase information into a sinusoidal value. Since phase
information maps directly into amplitude, the SIN ROM uses
the digital phase information as an address to a look-up table,
and converts the phase information into amplitude. Although
the NCO contains a 27-bit phase accumulator, the output of the
NCO is truncated to 12 bits. Using the full resolution of the
phase accumulator is impractical and unnecessary as this would
require a look-up table of 227 entries. It is necessary only to have
sufficient phase resolution such that the errors due to
truncation are smaller than the resolution of the 10-bitDAC.
This requires the SIN ROM to have two bits of phase resolution
more than the 10-bit DAC. The DDS includes a high impedance
current source 10-bit DAC.
RESPONSE STAGE The diagram below shows the input stage to pin TF1. Current
from the external sensor load flows through the TF1 pin and
into a transimpedance amplifier which has an external resistor
across its feedback. The user needs to choose a precision resistor
in the feedback loop such that the dynamic range of the ADC is
used. The positive node of the transimpedance amplifier is
biased to VDD/2. The output of the Transimpedance amplifier
can then be gained by either 1 or 5, and is fed directly into the
input of the ADC.
Figure 7.
ADC OPERATION The AD5934 has an integrated on board 12-bit ADC. The ADC
contains an on-chip track and hold amplifier, a successive
approximation A/D converter. Clocking for the A/D is provided
using a divided down ratio of the reference clock.
The A/D is a successive approximation analog to digital
converter, based on a Capacitive Dac design Architecture. The
figures below show simplified schematics of the ADC. The ADC
is comprised of control logic, a SAR, and a capacitive DAC, all
of which are used to add and subtract fixed amounts of charge
from the Sampling capacitor to bring the comparator back into
a balanced condition. The 1st figure shows the ADC during its
acquisition phase. SW2 is closed and SW1 is in position A, the
comparator is held in a balanced condition, and the sampling
capacitor acquires the signal on VA1, for example.
Figure 8.
When the ADC starts a conversion, SW2 will open and SW1
will move to position B, as shown below, causing the
comparator to become unbalanced. The control logic and the
capacitive DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is re-
balanced, the conversion is complete. The control logic
generates the ADC output code.
Figure 9.
The start conversion for the ADC is either user controlled via
an external adc_trig pin or can be internally programmed as a
delay from the start of the excitation signal. The data from the
ADC is directly available on the I2C interface or can either be
stored in a FIFO RAM until the entire frequency sweep is
completed.
DFT CONVERSION A Discrete Fourier Transform is calculated for each frequency
point in the sweep. The return signal is converted by the ADC,
windowed, and then multiplied with a test phasor value to give a
real and imaginary output. This is repeated for 1024 sample
points of the input signal and the results of each multiplication
summed to give a final answer as a complex number. The
resultant answer at each frequency is two 16-bit words, the real
and imaginary data in complex form.
Figure 10.
The DFT algorithm is represented by ))()()]njSinenxSUMfX−=
Both the real and imaginary data register have 15 bits of data
and one sign bit. The 15 bits of data are in 2’s compliment
format. The magnitude of the signal can be represented by Magnitude=
This returned magnitude is a scaled valued of the actual
complex impedance measured. The multiplication factor
between the magnitude returned and the actual impedance is
called the GAIN FACTOR. The user needs to then calculate this
GAIN FACTOR value and use it for calibration in the system.
REGISTER MAP The register map contains the registers where the frequency sweep data is loaded, and the resultant real and imaginary data is stored. Each
row equals 8 bits of data.
Table 4. Register Map
