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AD5933YRSZ
1 MSPS 12 Bit Impedance Converter, Network Analyzer
1 MSPS 12-Bit Impedance Converter,
Network Analyzer
Rev. PrA
FEATURES
50KHz Max Excitation Output
Impedance Range .1k-20M, 12 Bit Resolution
Selectable System Clock from the following:
PLL, RC Oscillator, External Clock
DSP Real and Imaginary Calculation (FFT)
3V Power Supply,
Programmable Sinewave Output
Frequency Resolution 27 Bits (<0.1Hz)
Frequency Sweep Capability
12 Bit Sampling ADC
ADC Sampling 1MSPS, INL +/- 1LSB Max.
On Chip Temp Sensor allows +/-2 oC accuracy
Serial I2C Loading
Temperature Range –40-125oC 16 SSOP
APPLICATIONS
Complex Impedance Measurement
Impedance Spectrometry
Biomedical and Automotive Sensors
Proximity Sensors
FFT Processing
GENERAL DESCRIPTION The AD5933 is a high precision impedance converter system
solution which combines an on board frequency generator with
a 12 Bit 1MSPS ADC. The frequency generator allows an
external complex impedance to be excited with a known
frequency. The response signal from the impedance is sampled
by the on board ADC and FFT processed by an on-board DSP
engine. The FFT algorithm returns a Real (R) and Imaginary (I)
data word, allowing impedance to be conveniently calculated.
The impedance magnitude and phase is easily calculated using
the following equations:
To determine the actual real impedance value Z(W) , generally a
frequency sweep is performed. The impedance can be
calculated at each point and a frequency vs magnitude plot can
be created.
The system allows the user to program a 2V PK-PK sinusoidal
signal as excitation to an external load. Output ranges of 1V,
500mV, 200mV can also be programmed. The signal is
provided on chip using DDS techniques. Frequency resolution
of 27 bits (less than 0.1HZ) can be achieved. The clock for the
DDS can be generated from an external reference clock, an
internal RC oscillator or an internal PLL. The PLL has a gain
stage of 512 and typically needs a reference clock of 32KHz on
the MCLK pin.
To perform the frequency sweep, the user must first program
the conditions required for the sweep; start frequency, delta
frequency, step frequency, etc. A Start Command is then
required to begin the sweep.
At each point on the sweep the ADC will take 1024 samples and
calculate a Discrete Fourier Transform to provide the real and
imaginary data for the waveform. The real and imaginary data
is available to the user through the 12C interface.
To determine the impedance of the load at any one frequency
point, Z(w), a measurement system comprised of a trans
impedance amplifier, gain stage and ADC are used to record
data. The gain stage for the response stage is 1 or 5.
The ADC is a low noise, high speed 1MSPS sampling ADC that
operates from a 3V supply. Clocking for both the DDS and
ADC signals is provided externally via the MCLK reference
clock, which is provided externally from a crystal oscillator. The
AD5933 is available in a 16 ld SSOP.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Characteristics.....................................................................5
Pin Configuration and function description................................6
General Description.........................................................................7
Output Stage..................................................................................7
Circuit Description.......................................................................7
Numerical Controlled Oscillator + Phase Modulator.............7
SIN ROM.......................................................................................8
Response Stage..............................................................................8
ADC Operation............................................................................8
DFT Conversion...........................................................................8
Temperature Sensor.....................................................................9
Register Map (Each Row equals 8 Bits of Data).........................11
Control Register..........................................................................13
Control Register Decode:..........................................................14
Initialize Sensor with Start Frequency.....................................14
Start Frequency Sweep...............................................................14
Increment Frequency.................................................................14
Repeat Frequency.......................................................................14
Power Down................................................................................14
Standby Mode.............................................................................14
Read Temperature......................................................................14
Error Checking...........................................................................14
RESET..........................................................................................14
System Clock...............................................................................14
Output Voltage............................................................................14
Post Gain.....................................................................................14
Performing a Frequency Sweep – Flow Chart............................15
Serial Bus Interface.....................................................................15
General I2C Timing....................................................................15
Writing/Reading to the AD5933..............................................16
Block Write..................................................................................17
AD5933 Read Operations.........................................................17
Error Correction.........................................................................18
P.E.C.............................................................................................18
Checksum....................................................................................18
User Command Codes..............................................................18
Outline Dimensions.......................................................................20
ESD Caution................................................................................20
REVISION HISTORY
12/04—Revision PrA—Preliminary Version SPECIFICATIONS VDD = +3.0 V +/- 10%, TMIN to TMAX unless otherwise noted.
Table 1.
Temperature ranges are as follows: B Version: –40°C to +125°C, typical at 25°C. Guaranteed by design and characterization, not production tested.
TIMING CHARACTERISTICS
Table 2. I2C Serial Interface SCL
SDA
STARTCONDITIONREPEATEDSTARTCONDITION
STOPCONDITION
Figure 1. I2C Interface Timing Diagram
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3.
GENERAL DESCRIPTION The AD5933 is a high precision impedance converter system
solution which combines an on board frequency generator with
a 12 Bit 1MSPS ADC. The frequency generator allows an
external complex impedance to be excited with a known
frequency. The response signal from the impedance is sampled
by the on board ADC and FFT processed by an on-board DSP
engine. The FFT algorithm returns two Real (R) and Imaginary
(I) data words. The impedance magnitude and phase is easily
calculated using the following equations:
To determine the actual real impedance value Z(W) , generally a
frequency sweep is performed. The impedance can be
calculated at each point and a frequency vs magnitude plot can
be created.
Figure 2.
The system allows the user to program a 2V PK-PK sinusoidal
signal as excitation to an external load. Output ranges of 1V,
500mV, 200mV can also be programmed. The signal is provided
on chip using DDS techniques. Frequency resolution of 27 bits
(less than 0.1HZ) can be achieved. The clock for the DDS can
be generated from an external reference clock, an internal RC
oscillator or an internal PLL. The PLL has a gain stage of 520
and typically needs a reference clock of 32KHz on the MCLK
pin.
OUTPUT STAGE The output stage of the AD5933, shown in diagram below,
provides a constant output frequency or frequency sweep
function which has a programmable output voltage of
2/1/0.5/0.2V. The frequency sweep sequence is pre-progammed
through the I2C interface. An I2C command is used to start the
excitation sequence.
Figure 3.
CIRCUIT DESCRIPTION The AD5933 has a fully integrated Direct Digital Synthesis
(DDS) core to generate required frequencies. The block requires
a reference clock to provide digitally created sine waves up to
50KHz. This is provided through an external reference clock,
MCLK. This clock is internally divided down by 4 to provide
the reference clock or fMCLK to the DDS.
The internal circuitry of the DDS consists of the following main
sections: a Numerical Controlled Oscillator (NCO), a
Frequency Modulator, SIN ROM and a Digital-to-Analog
Converter.
NUMERICAL CONTROLLED OSCILLATOR + PHASE
MODULATOR The main component of the NCO is a 27-bit phase accumulator
which assembles the phase component of the output signal.
Figure 4
Continuous time signals have a phase range of 0 to 2pi. Outside
this range of numbers, the sinusoid functions repeat themselves
in a periodic manner. The digital implementation is no
different. The accumulator simply scales the range of phase
numbers into a multi-bit digital word. The phase accumulator
in the DDS is implemented with 28 bits. Therefore, 2pi = 227.
Likewise, the DPhase term is scaled into this range of numbers
0 < DPhase < 227 – 1. Making these substitutions into the
equation above
f = DPhase x fMCLK/227
where 0 < DPhase < 227 - 1.
(Note. fmclk = MCLK/4)
The input to the phase accumulator (i.e., the phase step) is
selected from the frequency register. NCOs inherently generate
SIN ROM To make the output from the NCO useful, it must be converted
from phase information into a sinusoidal value. Since phase
information maps directly into amplitude, the SIN ROM uses
the digital phase information as an address to a look-up table,
and converts the phase information into amplitude. Although
the NCO contains a 27-bit phase accumulator, the output of the
NCO is truncated to 12 bits. Using the full resolution of the
phase accumulator is impractical and unnecessary as this would
require a look-up table of 227 entries. It is necessary only to
have sufficient phase resolution such that the errors due to
truncation are smaller than the resolution of the 10-bitDAC.
This requires the SIN ROM to have two bits of phase resolution
more than the 10-bit DAC. The DDS includes a high impedance
current source 10-bit DAC.
RESPONSE STAGE The diagram below shows the input stage to pin TF1. Current
from the external sensor load flows through the TF1 pin and
into a transimpedance amplifier which has an external resistor
across its feedback. The user needs to choose a precision
resistor in the feedback loop such that the dynamic range of the
ADC is used. The positive node of the transimpedance
amplifier is biased to VDD/2. The output of the
Transimpedance amplifier can then be gained by either 1 or 5,
and is fed directly into the input of the ADC.
Figure 5.
ADC OPERATION The AD5933 has an integrated on board 12 bit ADC. The ADC
contains an on-chip track and hold amplifier, a successive
approximation A/D converter. Clocking for the A/D is provided
using a divided down ratio of the reference clock.
The A/D is a successive approximation analog to digital
converter, based on a Capacitive DAC design Architecture. The
figures below show simplified schematics of the ADC. The ADC
is comprised of control logic, a SAR, and a capacitive DAC, all
of which are used to add and subtract fixed amounts of charge
from the Sampling capacitor to bring the comparator back into
a balanced condition. The 1st figure shows the ADC during its
acquisition phase. SW2 is closed and SW1 is in position A, the
Figure 6.
When the ADC starts a conversion, SW2 will open and SW1
will move to position B, as shown below, causing the
comparator to become unbalanced. The control logic and the
capacitive DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is re-
balanced, the conversion is complete. The control logic
generates the ADC output code.
Figure 7.
The start conversion for the ADC is either user controlled via
an external adc_trig pin or can be internally programmed as a
delay from the start of the exitation signal. The data from the
ADC is directly available on the I2C interface or can either be
stored in a FIFO RAM until the entire frequency sweep is
completed.
DFT CONVERSION A discrete Fourier transform is calculated for each frequency
point in the sweep. The return signal is converted by the ADC,
windowed and then multiplied with a test phasor value to give a
real and imaginary output. This is repeated for 1024 sample
points of the input signal and the results of each multiplication
summed to give a final answer as a complex number. The
resultant answer at each frequency is two 16 bit words, the real
and imaginary data in complex form.
Figure 8.
The DFT algorithm is represented by
X(f) = SUM x(n)[Cos(n)-jSine(n)]
Both the real and Imaginary data register have 15 bits of data
and one sign bit. The 15 bits of data are in 2’s compliment
format. The magnitude of the signal can be represented by
This magnitude that’s returned is a scaled valued of the actual
complex impedance measured. The multiplication factor
between the magnitude returned and the actual impedance is
called the GAIN FACTOR. The user needs to then calculate this
GAIN FACTOR value and use it for calibration in the system.
TEMPERATURE SENSOR The temperature sensor is a 13-bit digital temperature sensor
with a 14th bit that acts as a sign bit. The block houses an on-
chip temperature sensor, a 13-bit A/D converter and a reference
circuit. The A/D converter section consists of a conventional
successive-approximation converter based around a capacitor
DAC.
The on-chip temperature sensor allows an accurate measure-
ment of the ambient device temperature to be made. The
specified measurement range of the sensor is −40°C to +150°C.
At +150°C. The structural integrity of the device starts to
deteriorate when operated at voltage and temperature
maximum specifications.
Temperature Conversion Details The conversion clock for the part is internally generated; no
external clock is required except when reading from and writing
to the serial port. In normal mode, an internal clock oscillator
runs an automatic conversion sequence. During this automatic
conversion sequence, a conversion is initiated every 1 second. At
this time, the part powers up its analog circuitry and performs a
temperature conversion. This temperature conversion typically
when the 1 second timer times out and the next conversion
begins. The result of the most recent temperature conversion is
always available in the serial output register because the serial
interface circuitry never shuts down.
The temperature sensor block will default to a power-down
state. To perform a temperature measurement a command is
written to the control register. After the temperature operation
is complete, the block automatically powers down until the next
temperature command is issued.
In normal conversion mode, the internal clock oscillator is reset
after every read or write operation. This causes the device to
start a temperature conversion, the result of which is typically
available 800 µs later. Similarly, when the part is taken out of
shutdown mode, the internal clock oscillator is started and a
conversion is initiated. The conversion result is available 800 µs
later, typically. Reading from the device before a conversion is
complete causes the block to stop converting; the part starts
again when serial communication is finished.
Temperature Value Register The temperature value register is a 16-bit read-only register that
stores the temperature reading from the ADC in 13-bit twos
complement format plus a sign bit. The two MSB bits are don’t
cares. DB13 is the sign bit. The ADC can theoretically measure a
255°C temperature span. The internal temperature sensor is
guaranteed to a low value limit of –40°C and a high limit of
+150°C.
Table 4. Temperature Data Format
Temperature Conversion Formula 1. Positive Temperature = ADC Code(d)/32
2. Negative Temperature = (ADC Code*(d) – 16384)/32 *Using all 14 bits of the data byte, includes the sign bit. Negative Temperature = (ADC Code(d)* – 8192)/32
–40°C01, 0010, 1100, 0000
Figure 9. Temperature to Digital Transfer Function
