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AD5764ASU-AD5764BSU-AD5764CSU
Complete, Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output D/A Converter
Complete, Quad, 16-Bit, High Accuracy,
Serial Input, Bipolar Voltage Output DAC
Rev. PrC 21-Oct-04
FEATURES
Complete quad 16-bit D/A converter
Programmable output range: ±10 V, ±10.25 V, or ±10.5 V
±1 LSB max INL error, ±1 LSB max DNL error
Low noise : 60 nV/√Hz
Settling time: 10µs max
Integrated reference buffers
Internal reference, 10 ppm/°C
On-chip temp sensor, ±5°C accuracy
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via LDAC
Asynchronous CLR to zero code
Digital offset and gain adjust
Logic output control pins
DSP/microcontroller compatible serial interface
Temperature range:−40°C to +85°C
iCMOS™ Process Technology
APPLICATIONS
Industrial automation
Closed-loop servo control, process control
Data acquisition systems
Automatic Test Equipment
Automotive test and measurement
High accuracy instrumentation
GENERAL DESCRIPTION The AD5764 is a quad, 16-bit serial input, voltage output
digital-to analog converter that operates from supply voltages of
±12 V up to ±15 V. Nominal full-scale output range is ±10 V,
provided are integrated output amplifiers, reference buffers,
internal reference, and proprietary power-up/power-down
control circuitry. It also features a digital I/O port that may be
programmed via the serial interface, and an analog temperature
sensor. The part incorporates digital offset and gain adjust
registers per channel.
The AD5764 is a high performance converter that offers
guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB,
low noise and 10 µs settling time and includes an on-chip 5 V
reference with a reference tempco of 10 ppm/°C max. During
power-up (when the supply voltages are changing), Vout is
clamped to 0V via a low impedance path.
The AD5764 uses a serial interface that operates at clock rates up
to 30 MHz and is compatible with DSP and microcontroller
interface standards. Double buffering allows the simultaneous
updating of all DACs. The input coding is programmable to either
twos complement or straight binary formats. The asynchronous
clear function clears all DAC registers to either bipolar zero or
zero-scale depending on the coding used. The AD5764 is ideal for
both closed-loop servo control and open-loop control
applications. The AD5764 is available in a 32-lead TQFP package,
and offers guaranteed specifications over the −40°C to +85°C
industrial temperature range. See functional block diagram,
Figure 1.
iCMOS™ Process Technology
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a
technology platform that enables the development of analog ICs capable of 30V and operating at +/-15V supplies while allowing dramatic reductions in
power consumption and package size, and increased AC and DC performance.
TABLE OF CONTENTS Functional Block Diagram..............................................................3
Specifications.....................................................................................4
AC Performance Characteristics................................................6
Timing Characteristics................................................................7
Absolute Maximum Ratings..........................................................10
ESD Caution................................................................................10
Pin Configuration and Function Descriptions...........................11
Terminology....................................................................................13
Typical Performance Characteristics........Error! Bookmark not
defined. General Description.......................................................................15
dac architecture...........................................................................16
Reference Buffers........................................................................16
Serial interface............................................................................16
Simultaneous Updating Via LDAC..........................................17
transfer function.........................................................................18
Asynchronous Clear (CLR).......................................................18
Function Register.......................................................................20
DAta register...............................................................................21
Coarse gain register....................................................................21
Fine gain register........................................................................21
offset register...............................................................................22
AD5764 Features............................................................................23
Analog Output Control.............................................................23
Digital Offset and Gain Control...............................................23
Programmable Short-Circuit protection.................................23
Digital I/O Port...........................................................................23
Temperature Sensor...................................................................23
Local ground offset adjust.........................................................23
Outline Dimensions.......................................................................24
Ordering Guide..........................................................................28
REVISION HISTORY Revision PrC 21-Oct-04: Preliminary Version
FUNCTIONAL BLOCK DIAGRAM
LDACVREF CDTEMP
RSTINRSTOUTREFGND
AGNDD
VOUTD
AGNDC
VOUTC
AGNDB
VOUTB
AGNDA
VOUTA
ISCC
SDIN
SCLK
SYNC
SDO
BIN/2SCOMP
CLRPGND
DVCC
DGND04641-P
REFOUT
Figure 1. Functional Block Diagram
SPECIFICATIONS AVDD = +11.4 V to +15.75 V, AVSS = −11.4 V to −15.75 V, AGND = DGND = REFGND = PGND=0 V; REFAB = REFCD= 5 V Ext;
DVCC = 2.7 V to 5.5 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 1. 1 Temperature range −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance.
AC PERFORMANCE CHARACTERISTICS
AVDD = +11.4 V to +15.75 V, AVSS = −11.4 V to −15.75 V, AGND = DGND = REFGND = PGND=0 V; REFAB = REFCD= 5 V Ext;
DVCC = 2.7 V to 5.5 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and
characterization, not production tested.
Table 2.
TIMING CHARACTERISTICS
AVDD = +11.4 V to +15.75 V, AVSS = −11.4 V to −15.75 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD= 5 V Ext;
DVCC = 2.7 V to 5.5 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
7 Guaranteed by design and characterization. Not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
9 See Figure 2, Figure 3, and Figure 4. Stand-alone mode only.
11 Measured with the load circuit of Figure 5. Daisy-chain mode only.
DB23
SCLK
SYNC
SDIN
LDAC
VOUT
LDAC = 0
VOUT
CLR
VOUT24
DB0t5t2
t12
t11
t12
t11t10
t13
t14
04641-P
-002
Figure 2. Serial Interface Timing Diagram
LDAC
SDO
SDIN
SYNC
SCLK
SDO
SDIN
SYNC
SCLK
SELECTED REGISTER DATA
CLOCKED OUT
UNDEFINED
NOP CONDITIONINPUT WORD SPECIFIES
REGISTER TO BE READ
04641-P
Figure 4. Readback Timing Diagram
200µAIOL
200µAIOH
VOH (MIN) OR
VOL (MAX)TO OUTPUT
PINCL
50pF
04641-P
Figure 5. Load Circuit for SDO Timing Diagram
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Transient currents of up to 100 mA will not cause SCR latch-up.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5764
TOP VIEW
(Not to Scale)
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
TOUT
TIN
DGND
PGN
ISCC
BIN/2
OMP
TEMPRE
FGND
FOUT
FCD
FAB
PIN 1INDICATOR
04641-P
Figure 6. 32-Lead TQFP Pin Configuration Diagram
Table 5. Pin Function Descriptions
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or Integral Nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure .
Differential Nonlinearity
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure .
Monotonicity
A DAC is monotonic, if the output either increases or remains
constant for increasing digital input code. The AD5764 is
monotonic over its full operating temperature range
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (Straight Binary coding) or 0x0000
(2sComplement coding)
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (FFFF Hex) is loaded to the DAC register. Ideally the
output should be programmed full scale value – 1 LSB. Full-
scale error is expressed in percent of full-scale range. A plot of
full-scale error vs. temperature can be seen in Figure .
Negative Full-Scale Error / Zero Scale Error
Negative full-scale error is the error in the DAC output voltage
when 0x0000 (Straight Binary coding) or 0x8000
(2sComplement coding) is loaded to the DAC register. Ideally
the output voltage should be programmed negative full scale
value – 1 LSB.
Output Voltage Settling Time
Output voltage settling time is the amount od time it takes for
the output to settle to a specified level for a full-scale input
change.
Slew Rate
The slew rate of a device is a limatation in the rate of change of
amplifierused at its output. Slew rate is measured from 10% to
90% of the output signal and is given in Vµs.
Gain Error
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
Total Unadjusted Error
Total Unadjusted Error (TUE) is a measure of the output error
taking all the various errors into account. A typical TUE vs.
code plot can be seen in Figure .
Zero-Code Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV secs
and is measured when the digital input code is changed by
1 LSB at the major carry transition (7FFF Hex to 8000 Hex). See
Figure .
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV secs and measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa.
Power Supply Sensitivity
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage.
DC Crosstalk
This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in µV.
due to a digital code changeand subsequent output change of
another DAC. This includes both digital and anlalog crosstalk.
It is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with /LDAC low and
monitoring the output of another DAC. The energy of the glitch
is expressed in nV-s.
Channel-to-Channel Isolation
This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC.
It is measured in dB.
