AD573JN ,10-Bit A/D ConverterSpecifications subject to change without notice.
AD573KD ,10-Bit A/D ConverterFEATURES FUNCTIONAL BLOCK DIAGRAMComplete 10-Bit A/D Converter with Reference, ClockDIGITALand Comp ..
AD573KN ,10-Bit A/D Converterspecifications.output buffers.The AD573 is available in two versions for the 0°C to +70°Ctemperatur ..
AD573SD ,10-Bit A/D ConverterSpecifications shown in boldface are tested on all production units at final electrical test. Resul ..
AD574 ,Complete 12-Bit A/D ConverterSPECIFICATIONS unless otherwise noted) AD574AJ AD574AK AD574ALM ..
AD574AJ ,Complete 12-Bit A/D ConverterSpecifications appear in the Timing Section.212/8 Input is not TTL-compatible and must be hard wire ..
AD9765AST ,12-Bit, 125 MSPS Dual TxDAC+ D/A ConverterSPECIFICATIONSMIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 12 Bits1DC ACCURACYIntegral Linear ..
AD9765ASTZ , 10-/12-/14-Bit, 125 MSPS Dual TxDAC Digital-to-Analog Converters
AD9765ASTZ , 10-/12-/14-Bit, 125 MSPS Dual TxDAC Digital-to-Analog Converters
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AD9768JD ,Ultrahigh Speed IC D/A ConverterSPECIFICATIONSinput levels; nominal power supplies; R = 50 V; R = 220 V; V = 0 V)L SET RETParameter ..
AD9768SD ,Ultrahigh Speed IC D/A ConverterGENERAL DESCRIPTIONThe Analog Devices AD9768SD D/A converter is a monolithiccurrent-output converte ..
AD573JD-AD573JN-AD573KD-AD573KN-AD573SD
10-Bit A/D Converter
FUNCTIONAL BLOCK DIAGRAMREV.A
10-Bit A/D Converter
FEATURES
Complete 10-Bit A/D Converter with Reference, Clock
and Comparator
Full 8- or 16-Bit Microprocessor Bus Interface
Fast Successive Approximation Conversion—20 ms typ
No Missing Codes Over Temperature
Operates on +5 V and –12 V to –15 V Supplies
Low Cost Monolithic Construction
PRODUCT DESCRIPTIONThe AD573 is a complete 10-bit successive approximation
analog-to-digital converter consisting of a DAC, voltage refer-
ence, clock, comparator, successive approximation register
(SAR) and three state output buffers—all fabricated on a single
chip. No external components are required to perform a full
accuracy 10-bit conversion in 20 μs.
The AD573 incorporates advanced integrated circuit design and
processing technologies. The successive approximation function
is implemented with I2L (integrated injection logic). Laser trim-
ming of the high stability SiCr thin-film resistor ladder network
insures high accuracy, which is maintained with a temperature
compensated subsurface Zener reference.
Operating on supplies of +5 V and –12 V to –15 V, the AD573
will accept analog inputs of 0 V to +10 V or –5 V to +5 V. The
trailing edge of a positive pulse on the CONVERT line initiates
the 20 μs conversion cycle. DATA READY indicates completion
of the conversion. HIGH BYTE ENABLE (HBE) and LOW
BYTE ENABLE (LBE) control the 8-bit and 2-bit three state
output buffers.
The AD573 is available in two versions for the 0°C to +70°C
temperature range, the AD573J and AD573K. The AD573S
guarantees ±1 LSB relative accuracy and no missing codes from
–55°C to +125°C.
Three package configurations are offered. All versions are offered
in a 20-pin hermetically sealed ceramic DIP. The AD573J and
AD573K are also available in a 20-pin plastic DIP or 20-pin
leaded chip carrier.
*. Patent Nos. 3,940,760; 4,213,806; 4,136,349; 4,400,689;
and 4,400,690.
PRODUCT HIGHLIGHTSThe AD573 is a complete 10-bit A/D converter. No external
components are required to perform a conversion.The AD573 interfaces to many popular microprocessors
without external buffers or peripheral interface adapters. The
10 bits of output data can be read as a 10-bit word or as 8-
and 2-bit words.The device offers true 10-bit accuracy and exhibits no miss-
ing codes over its entire operating temperature range.The AD573 adapts to either unipolar (0 V to +10 V) or
bipolar (–5 V to +5 V) analog inputs by simply grounding or
opening a single pin.Performance is guaranteed with +5 V and –12 V or –15 V
supplies.The AD573 is available in a version compliant with MIL-STD-
883. Refer to the Analog Devices Military Products Data-
book or current /883B data sheet for detailed specifications.
AD573–SPECIFICATIONS
(@ TA = +258C, V+ = +5 V, V– = –12 V or –15 V, all voltages measured with respect
to digital common, unless otherwise noted.)DIFFERENTIAL NONLINEARITY
POWER SUPPLY REJECTION
LOGIC INPUTS
CONVERSION TIME
POWER SUPPLY
OPERATING CURRENT
NOTESRelative accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the zero to the full scale of the device.Full-scale calibration is guaranteed trimmable to zero with an external 50 Ω potentiometer in place of the 15 Ω fixed resistor. Full scale is defined as 10 volts minus
1 LSB, or 9.990 volts.Defined as the resolution for which no missing codes will occur.Change from +25°C value from +25°C to TMIN or TMAX.The data output lines have active pull-ups to source 0.5 mA. The DATA READY line is open collector with a nominal 6 kΩ internal pull-up resistor.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGSV+ to Digital Common . . . . . . . . . . . . . . . . . . . . .0 V to +7 V
V– to Digital Common . . . . . . . . . . . . . . . . . . .0 V to –16.5 V
Analog Common to Digital Common . . . . . . . . . . . . . . .±1 V
Analog Input to Analog Common . . . . . . . . . . . . . . . . .±15 V
Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to V+
Digital Outputs (High Impedance State) . . . . . . . . . .0 V to V+
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . .800 mW
ORDERING GUIDE1NOTESFor details on grade and package offerings screened in accordance with MIL-STD-883, refer to Analog Devices Military
Products Databook.D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.
FUNCTIONAL DESCRIPTIONA block diagram of the AD573 is shown in Figure 1. The posi-
tive CONVERT pulse must be at least 500 ns wide. DR goes
high within 1.5 μs after the leading edge of the convert pulse
indicating that the internal logic has been reset. The negative
edge of the CONVERT pulse initiates the conversion. The in-
ternal 10-bit current output DAC is sequenced by the integrated
injection logic (I2L) successive approximation register (SAR)
from its most significant bit to least significant bit to provide an
output current which accurately balances the input signal cur-
rent through the 5 kΩ resistor. The comparator determines
whether the addition of each successively weighted bit current
causes the DAC current sum to be greater or less than the input
current; if the sum is more, the bit is turned off. After testing all
bits, the SAR contains a 10-bit binary code which accurately
represents the input signal to within 1/2 LSB (0.05% of full scale).
The SAR drives DR low to indicate that the conversion is com-
plete and that the data is available to the output buffers. HBE
and LBE can then be activated to enable the upper 8-bit and
lower 2-bit buffers as desired. HBE and LBE should be brought
high prior to the next conversion to place the output buffers in
the high impedance state.
The temperature compensated buried Zener reference provides
the primary voltage reference to the DAC and ensures excellent
stability with both time and temperature. The bipolar offset in-
put controls a switch which allows the positive bipolar offset
current (exactly equal to the value of the MSB less 1/2 LSB) to
be injected into the summing (+) node of the comparator to
offset the DAC output. Thus the nominal 0 V to +10 V unipolar
input range becomes a –5 V to +5 V range. The 5 kΩ thin-film
input resistor is trimmed so that with a full-scale input signal, an
input current will be generated which exactly matches the DAC
Figure 1.Functional Block Diagram
UNIPOLAR CONNECTIONThe AD573 contains all the active components required to per-
form a complete A/D conversion. Thus, for many applications,
all that is necessary is connection of the power supplies (+5 V
and –12 V to –15 V), the analog input and the convert pulse.
However, there are some features and special connections which
should be considered for achieving optimum performance. The
functional pinout is shown in Figure 2.
The standard unipolar 0 V to +10 V range is obtained by short-
ing the bipolar offset control pin (Pin 16) to digital common
(Pin 17).
AD573
LSB DB0
DIG COM
LBE
HBE
DB1
DB2
DB3
ANALOG IN
ANALOG COM
BIP OFFDB4
DB5
DB6
DB7
DB8
MSB DB9V+
CONVERTFigure 2. AD573 Pin Connections
Full-Scale CalibrationThe 5 kΩ thin-film input resistor is laser trimmed to produce a
current which matches the full-scale current of the internal
DAC—plus about 0.3%—when an analog input voltage of 9.990
volts (10 volts – 1 LSB) is applied at the input. The input resis-
tor is trimmed in this way so that if a fine trimming potentiom-
eter is inserted in series with the input signal, the input current
at the full-scale input voltage can be trimmed down to match
the DAC full-scale current as precisely as desired. However, for
many applications the nominal 9.99 volt full scale can be
achieved to sufficient accuracy by simply inserting a 15 Ω resis-
tor in series with the analog input to Pin 14. Typical full-scale
calibration error will then be within ±2 LSB or ±0.2%. If more
precise calibration is desired, a 50 Ω trimmer should be used
instead. Set the analog input at 9.990 volts, and set the trimmer
so that the output code is just at the transition between
11111111 10 and 11111111 11. Each LSB will then have a
weight of 9.766 mV. If a nominal full scale of 10.24 volts is de-
sired (which makes the LSB have a weight of exactly 10.00 mV),
a 100 Ω resistor and a 100 Ω trimmer (or a 200 Ω trimmer with
good resolution) should be used. Of course, larger full-scale
ranges can be arranged by using a larger input resistor, but lin-
earity and full-scale temperature coefficient may be compro-
mised if the external resistor becomes a sizeable percentage of
5 kΩ. Figure 3 illustrates the connections required for full-scale
calibration.
Figure 3.Standard AD573 Connections
Unipolar Offset CalibrationFigure 4a shows how the converter zero may be offset by up to
±3 bits to correct the device initial offset and/or input signal
offsets. As shown, the circuit gives approximately symmetrical
adjustment in unipolar mode.
Figure 4a. Figure 4b.
Figure 4.Offset Trims
Figure 5 shows the nominal transfer curve near zero for an
AD573 in unipolar mode. The code transitions are at the edges
of the nominal bit weights. In some applications it will be pref-
erable to offset the code transitions so that they fall between the
nominal bit weights, as shown in the offset characteristics.
Figure 5.AD573 Transfer Curve—Unipolar Operation
(Approximate Bit Weights Shown for Illustration, Nominal
Bit Weights ~ 9.766 mV)
This offset can easily be accomplished as shown in Figure 4b. At
balance (after a conversion) approximately 2 mA flows into the
Analog Common terminal. A 2.7 Ω resistor in series with this
terminal will result in approximately the desired 1/2 bit offset of
the transfer characteristics. The nominal 2 mA Analog Common
current is not closely controlled in manufacture. If high accu-
racy is required, a 5 Ω potentiometer (connected as a rheostat)
can be used as R1. Additional negative offset range may be ob-
tained by using larger values of R1. Of course, if the zero transi-
tion point is changed, the full-scale transition point will also
move. Thus, if an offset of 1/2 LSB is introduced, full-scale
trimming as described on the previous page should be done with
an analog input of 9.985 volts.
NOTE:During a conversion, transient currents from the Analog
Common terminal will disturb the offset voltage. Capacitive
decoupling should not be used around the offset network. These
transients will settle appropriately during a conversion. Capaci-
tive decoupling will “pump up” and fail to settle resulting in
conversion errors. Power supply decoupling, which returns to
BIPOLAR CONNECTIONTo obtain the bipolar –5 V to +5 V range with an offset binary
output code, the bipolar offset control pin is left open.
A –5.000 volt signal will give a 10-bit code of 00000000 00; an
input of 0.000 volts results in an output code of 10000000 00
and +4.99 volts at the input yields the 11111111 11 code. The
nominal transfer curve is shown in Figure 6.
Figure 6.AD573 Transfer Curve— Bipolar Operation
Note that in the bipolar mode, the code transitions are offset
1/2 LSB such that an input voltage of 0 volts ±5 mV yields the
code representing zero (10000000 00). Each output code is then
centered on its nominal input voltage.
Full-Scale CalibrationFull-Scale Calibration is accomplished in the same manner as in
unipolar operation except the full scale input voltage is +4.985
volts.
Negative Full-Scale CalibrationThe circuit in Figure 4a can also be used in bipolar operation to
offset the input voltage (nominally –5 V) which results in the
00000000 00 code. R2 should be omitted to obtain a symmetri-
cal range.
The bipolar offset control input is not directly TTL compatible
but a TTL interface for logic control can be constructed as
shown in Figure 7.
Figure 7. Bipolar Offset Controlled by Logic Gate
Gate Output = 1Unipolar 0–10 V Input Range
Gate Output = 0Bipolar ±5 V Input Range
SAMPLE-HOLD AMPLIFIER CONNECTION TO THE
AD573Many situations in high speed acquisition systems or digitizing
rapidly changing signals require a sample-hold amplifier (SHA)
in front of the A/D converter. The SHA can acquire and hold a
signal faster than the converter can perform a conversion. A
SHA can also be used to accurately define the exact point in
time at which the signal is sampled. For the AD573, a SHA can
also serve as a high input impedance buffer.
Figure 8 shows the AD573 connected to the AD582 monolithic
SHA for high speed signal acquisition. In this configuration, the
AD582 will acquire a 10 volt signal in less than 10 μs with a
droop rate less than 100 μV/ms.
Figure 8.Sample-Hold Interface to the AD573
DR goes high after the conversion is initiated to indicate that
reset of the SAR is complete. In Figure 8 it is also used to put
the AD582 into the hold mode while the AD573 begins its con-
version cycle. (The AD582 settles to final value well in advance
of the first comparator decision inside the AD573).
DR goes low when the conversion is complete placing the
AD582 back in the sample mode. Configured as shown in Fig-
ure 8, the next conversion can be initiated after a 10 μs delay to
allow for signal acquisition by the AD582.
Observe carefully the ground, supply, and bypass capacitor con-
nections between the two devices. This will minimize ground
noise and interference during the conversion cycle.
GROUNDING CONSIDERATIONSThe AD573 provides separate Analog and Digital Common
connections. The circuit will operate properly with as much as
±200 mV of common-mode voltage between the two commons.
This permits more flexible control of system common bussing
and digital and analog returns.
In normal operation, the Analog Common terminal may gener-
ate transient currents of up to 2 mA during a conversion. In ad-
dition a static current of about 2 mA will flow into Analog
Common in the unipolar mode after a conversion is complete.
The Analog Common current will be modulated by the varia-
tions in input signal.
AD573
CONTROL AND TIMING OF THE AD573The operation of the AD573 is controlled by three inputs:
CONVERT, HBE and LBE.
Starting a ConversionThe conversion cycle is initiated by a positive going CONVERT
pulse at least 500 ns wide. The rising edge of this pulse resets
the internal logic, clears the result of the previous conversion,
and sets DR high. The falling edge of CONVERT begins the
conversion cycle. When conversion is completed DR returns
low. During the conversion cycle, HBE and LBE should be held
high. If HBE or LBE goes low during a conversion, the data
output buffers will be enabled and intermediate conversion re-
sults will be present on the data output pins. This may cause
bus conflicts if other devices in a system are trying to use the bus.
VIH + VIL
CONVERTFigure 9.Convert Timing
Reading the DataThe three-state data output buffers are enabled by HBE and
LBE. Access time of these buffers is typically 150 ns (250 maxi-
mum). The data outputs remain valid until 50 ns after the en-
able signal returns high, and are completely into the high
impedance state 100 ns later.
LBE OR HBEtDD
HIGH
HIGHDB0–DB7
DB8–DB9Figure 10.Read Timing
TIMING SPECIFICATIONS (All grades, TA = TMIN–TMAX)
MICROPROCESSOR INTERFACE CONSIDERATIONS—
GENERALWhen an analog-to-digital converter like the AD573 is inter-
faced to a microprocessor, several details of the interface must
be considered. First, a signal to start the converter must be gen-
erated; then an appropriate delay period must be allowed to pass
before valid conversion data may be read. In most applications,
the AD573 can interface to a microprocessor system with little
pulse, and gating it with RD to enable the output buffers. The
use of a memory address and memory WR and RD signals de-
notes “memory-mapped” I/O interfacing, while the use of a
separate I/O address space denotes “isolated I/O” interfacing. In
8-bit bus systems, the 10-bit AD573 will occupy two locations
when data is to be read; therefore, two (usually consecutive) ad-
dresses must be decoded. One of the addresses can also be used
as the address which produces the CONVERT signal during
WR operations.
Figure 11 shows a generalized diagram of the control logic for
an AD573 interfaced to an 8-bit data bus, where two addresses
(ADC ADDR and ADC ADDR + 1) have been decoded. ADC
ADDR starts the converter when written to (the actual data be-
ing written to the converter does not matter) and contains the
high byte data during read operations. ADC ADDR + 1 per-
forms no function during write operations, but contains the low
byte data during read operations.
Figure 11.General AD573 Interface to 8-Bit Microprocessor
In systems where this read-write interface is used, at least 30
microseconds (the maximum conversion time) must be allowed
to pass between starting a conversion and reading the results.
This delay or “timeout” period can be implemented in a short
software routine such as a countdown loop, enough dummy in-
structions to consume 30 microseconds, or enough actual useful
instructions to consume the required time. In tightly-timed sys-
tems, the DR line may be read through an external three-state
buffer to determine precisely when a conversion is complete.
Higher speed systems may choose to use DR to signal an inter-
rupt to the processor at the end of a conversion.
