AD572AD ,12-BIT SUCCESSIVE APPROXIMATION INTEGRATED CIRCUIT A/D CONVERTERCHARACTERISTICS
Goin Em (Non 2) 20.05% FSR (Adi to Zero) * I
Unipolat Other Error t0.iB% FSR (Mi ..
AD572BD ,12-BIT SUCCESSIVE APPROXIMATION INTEGRATED CIRCUIT A/D CONVERTERcharacteristics and operating temperature
nnget; the "A" and "B" are specified from -25°C to +85°C ..
AD573JD ,10-Bit A/D ConverterSPECIFICATIONSto digital common, unless otherwise noted.) AD573J AD573K AD573SModel Min Typ Max ..
AD573JN ,10-Bit A/D ConverterSpecifications subject to change without notice.
AD573KD ,10-Bit A/D ConverterFEATURES FUNCTIONAL BLOCK DIAGRAMComplete 10-Bit A/D Converter with Reference, ClockDIGITALand Comp ..
AD573KN ,10-Bit A/D Converterspecifications.output buffers.The AD573 is available in two versions for the 0°C to +70°Ctemperatur ..
AD9764ARU ,14-Bit, 125 MSPS TxDAC D/A ConverterFEATURESMember of Pin-Compatible TxDAC Product Family+5V125 MSPS Update Rate0.1mF14-Bit ResolutionE ..
AD9765AST ,12-Bit, 125 MSPS Dual TxDAC+ D/A ConverterSPECIFICATIONSMIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 12 Bits1DC ACCURACYIntegral Linear ..
AD9765ASTZ , 10-/12-/14-Bit, 125 MSPS Dual TxDAC Digital-to-Analog Converters
AD9765ASTZ , 10-/12-/14-Bit, 125 MSPS Dual TxDAC Digital-to-Analog Converters
AD9767AST ,14-Bit, 125 MSPS Dual TxDAC+ D/A ConverterSPECIFICATIONSMIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 14 Bits1DC ACCURACYIntegral Linear ..
AD9768JD ,Ultrahigh Speed IC D/A ConverterSPECIFICATIONSinput levels; nominal power supplies; R = 50 V; R = 220 V; V = 0 V)L SET RETParameter ..
AD572AD-AD572BD
12-BIT SUCCESSIVE APPROXIMATION INTEGRATED CIRCUIT A/D CONVERTER
ANALOG
DEVICES
lMit Successive Approximation
Integrated Circuit MI Converter
AD572*
FEATURES
PERFORMANCE
True 12oBlt Operation: Max Nonlinnrlty <10.o12%
Low Gain T.c.: < " ppmPC (A0928)
Low Power: 900 mW
Fest Convenlon Time: < 25 pa
Monatonle Feedback DAC Guarantee: No Mining
VERSAnLrl'Y
Aerospace Temperature Range:
451: to +125“: MOSHE)
PoeItlw-Tm Serial or Parallel Logic Outputs
Short-Cyelo Capability
Predator: +10 V Refenneo for Enema! Application
Internal Buffer Amplimr
High Reliability Package
GENERAL DESCRIPTION
The ADS72 is a complete 12-bit successive approximation
tttuhm-tttdigital converter that includes an internal clock, refer-
ence, comparator, and buffer "tplifier, Its hybrid IC design
utilizes MSI digital and linear monolithic chips and active laser
trimming of high-stability thin-film resistors to provide superior
performance, flexibility and ease of use, combined with IC size,
price, and reliability.
Important performance characteristics of the ADS72 include I
maximum linearity error at 25'C of $031296, gain T.C. below
15 ppafC, typical power dissipation of 900 mW, and convert
sion time of less than 25 us. Of considerable significance in
umpaoe applications is the guaranteed performance from
-wc to +125% of the ADS7ZS. Monotonic operation of the
feedback Dlh converter guarantees no missing output codes
over temperature ranges of tt% to +70°C, --28'C to +85'C, and
-55°C to +125'C.
The design of the ADS72 includes scaling resistors that provide
male; input signal ranges of t.2.S, :10, tio, O to +5. or 0 to
+10 volts. Adding flexihility and value at: the + IO ll precision
reference, which also can be used for external applications, and
the input butler tunplirtet. All digital signals are fully TTL com-
patible, and the data output is positive-true and available in ei.
ther serial or parallel form.
The A0572 is available in three versions with differing guaran-
teed performance characteristics and operating temperature
ranget; the "A" and "B" are specified horn -25'C to +8YC,
and the 'S'' from -55°C to +125°C.
hitched by us. PM! Not. 3361.126; 3,803,590; ud 3.747.038.
REV. A
Infarmetlon fumished by Analog Devices is believed to be accurate and
reliable. However, no meponsitsillty is assumed by Analog Device: for "
use. not for eny infringements of patents or other rights of third parties
which may result from it: use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
ADS72 FUNCTIONAL BLOCK DIAGRAM
o'triil,,,,,si,,
East I-isliilseltitt
PRODUCT DESCRIPTION
The ADS72 functional diagram and pinout are shown above.
The device consists of the following monolithic bipolar circuit
elements:
1. Twelve-bit sneeessive-approximation register
. Twelve-bit DAC
. Low-drift comparator
. High-impedance buffer follower
4. Tempexature-omnpensated precision +10 V reference
6. Gated clock and digital control circuits
The +10 V reference is derived from a low drift Zener reference
diode which has its Tenet voltage amplir1ed and buffered by an
op amp. The reference voltage is calibrated to +10 V, :10 mV,
by active lam trimming of tttin-im resistors.
The DAC chip uses 12 precision, high speed bipolar current
steering switches, a control amplifier and a laser-trimmed thin-
film resistor network to produce a very fast, high accuracy ana.
log output current. The DAC is laser-tn'mmed to calibrate all
bit ratio scale factors to a precision of 0.005% of FSR (full-scale
range) to guarantee no missing codes over the appropriate tern"
perature ranges specifeed for the AD572A, AD572B, and
AD572S versions.
Different unipolar and bipolar analog input ranges can be se-
lected by changing connections at the device terminal pins. The
analog voltage input can be applied to either of the span (direct
input) resistors. Alternatively, the unity gain buffer follower can
be connected between the analog signal and either direct input
terminal when a high impedance input is required.
One l'oehnology War, PD. Box 9106, Norwood, MA 02062-0106. U.S.A.
Tel: 61113194700 Fax: 617/326-8703 wa: 710/390-0517
hlu: 920481 Cable: ANALOG NORWOODMASS
A0572 -- SPECIFI CATIONS (typical @ +25°c. t15 V and +5 If unless ('llTi'' noted)
Model numb ADMZBD ADS7ZSD
RESOLUTION 12 Bin . I
ANALOG INPUTS
Venus: Ranges
Bipolar 21.5, Md), 110.0 V . '
Unipolu ow+s.mo+mv . .
tttqerimtxtDirect Input)
OuH-SV.=2.5V 1.5m . .
0m‘lOV,:SV Men . .
:10 V 10 kit . .
Bulk: Amplifier
mm (mm) 100 Mtt . .
Bit: Current $0 nA . .
Settling Time
to 0.01%MFSR forZOVSlep Ips . .
DIGITAL INPUTS
Convert Commune! Note 1 . .
Logic landing 1 TTI. Load . .
TRANSFER CHARACTERISTICS
Gain Em: (Note 2) 20.05% FSR (Adi to Zero) I I
Unipolar Ofhet Em: :(msos FSR (Mi to Terry) ' .
lip!!! Otha Elm 0.I96 FMt (Adi to bro) * '
Linearity Em: (mu) :0.0|2% FSR . '
lnbemn Quatttimtiat Error tll LSB . *
Ditkmtttial Lima'ty Em: 21/2 ISB . .
No Mining Coda Gummwd: tt% to +70°C Guaranteed: -25‘C to +85’C Gummeed: -syc to +125°C
Pom Sum Sensitivity
tl5 V 30.00% FSWV‘ ' .
" ll $0.00”: FSWW I .
TEMPERATURE COEFFICIENTS
Gcin (Inn) :30 ppnt'C (-ZS’C to +890 :15 ppml'C (-15% to +85'C) :15 pptrfct-25'C to +8512)
:25 ppm (-5912 to 4 IIS‘C)
Uniwlu Offset :3 ppm FSRI'C :5 ppm FSRI‘C (mu) "
Bipolu Olin (aux) :1: ppm FSW'C :7 ppm FSRI'C "
Linearity :3 ppm F8RPC :2 ppm PSRI'C "
CONVERSION TIME (um) 25 M . .
DIGITAL OUTPUTS (An Coda Podu've-Twc)
hnud Dem
mum Code Binuy ' I
Bipdu Oak Ofha Bimryfl'wo: 1'axnplamnt . I
Output Drive I m Loads ' '
Serial Dan (NR2 format)
Unipohr Cod: Binary . .
Bipolar God: om Binary . .
Output Drive 2 TTI. Land: . .
§ng Logic "l" during Convmion . '
Sam Logic 'W' during Comm . .
Output Driw 2 TTL Load: . .
lumal Clock
Output Drive 2 TTI. Loads * .
quucncy 500 kHz . .
INTERNAL REFERENCE VOLTAGE t 10.00 V, tlt) mV xyp . .
Max Emu! Current tl ttth . *
Volta: Temperature thettitiettt (max) +20 mrst'C :10 ppme .
POWER REQUIREMENTS
Supply 1h2arslthtrresas ' IS V, 2595 6' +25 M (40 max) . .
-15 V, 25966:} -20mA(35 max) . .
+5V,:S%@ +80mA(l$0 mu) . .
Tool Pom Dissipudon 925 mW . .
TEMPERATURE RANGE .
Spediiestion -25‘C m "rc . 3S'Cto +IZS°C
Operating 45°C to + WN.' . '
Statue -55‘C to +1301: ' *
‘Sune speeitUtiort u ADSTZAD.
“Sun: stttrifiettiorts us ADSHBD.
Note 1 Positive pulse an as wide (min). Leading edge (hr' to "1") rem; registers. Trailing edge Cl'' w "O'') initiates conversion.
Note wmson. I%firedtesirtnrirtplacedthittAdiustixmsteFigutes4md$,
specitiratiom subject to change without notice.
REV. A
Applying the A0572
ORDERING GUIDE
Speeitieation Max Max Guaranteed Temp Range Package
Model Temp Range Gain TC Reference TC No Missing Codes Option'
ADS72AD -25°c to +ss°c t30 ppm/T t20 ppmré trc to +hrC DH-szc
ADS7ZBD -25°C to +85''C :15 ppmPC. t10 pmeC --25''C to +85'C DH-MC
ADVISD -SS’C to +125'C :15 ppmft (-2S't to +85°C) t20 pmeC -SST, to +125‘C DH-nc
:25 ppme (-55°C to +125°C) _
AD572SDAllBB Meets all specifications after processing to the requirements of M1L-STD-883, Method 5008, Class B.
Refer to Analog. Devices Military Datebook for details.
'DH-JZC " Six: Brand thmaic Dip for Hybrid (Medium Cavity).
d...', -
tfitgil,!l,,,,,
ll! IL.)
11-." W! . mumm-
"ttteNtt
etoeat
"AIY I.
m .AII
‘IJIT ttV
g r, E g
sh 3: "t it i, s'e,.uii'i
Figure h A0572 Functional Diagram and Pinout
THEORY OF OPERATION
On receipt of a CONVERT START command. the A0572 con-
verts the voltage " its analog input into en equivalent 12-bit
binary number. This conversion is accomplished as follows:
The 12-bit 'tses-ive-approximation register (SAR) has its lb
bit outputs eonneaed both to the respective device bit output
pins and to the corresponding bit inputs of the feedback DAC.
The analog input is successively compared to the feedback DAC
output, one bit It a time (MSB first, LSB last). The decision to
keep or reject each bit is made at the crmpletiort.of each bit
comparison period, depending on the state of the comparator at
that time.
TIMING
The timing diagram is shown in Figure 2. Receipt of a CON-
VERT START signal set: the STATUS flag, indicating conver-
sion in progress. This, in mm, temoves the inhibit applied to
the med clock, permitting it to ma throagh 13 cycles. All SAR
parallel bit and STATUS f1ip41ops ere initialized on the leading
edge, and the gated clock inhibit signal is removed on the trail-
REV. A
ing edge of the CONVERT START signal. At time to, B, is
reset and B, -ih, are set unconditionally. At t, the Bit 1 deci-
sion is made (keep or reject) and Bit 2 is unconditionally reset.
At te, the Bit 2 decision is made and Bit 3 is reset uncondition-
ally. This sequence continues until the Bit 12 (LSB) decision is
made at tn. After a 100 ns delay period, the STATUS flag is
met, indicating that the conversion is complete and that the
parallel output data is valid. Resetting the STATUS ilag restores
the gated clock inhibit signal, forcing the clock output to the
logic "O" state.
Corresponding serial and parallel data bits become valid on the
same positive-going clock edge. Serial data does ttot change and
is gmmteed valid on negative-going clock edges. Serial data
an be transferred by clocking it into a receiving shift register
on these edges.
Incorporation of the 100 ns delay period guarantees that the par-
allel (and serial) data are valid at the Logic "l" to "o" transition
of the STATUS flair, permitting parallel data transfer to be initi-
ated by the trailing edge of the STATUS signal.
RNRLOG DEUICES FHX‘ON'DEHRND HOTLINE - Page 5
'OH-m-I
i'r'l'l'P' - l 11.
t"''--t
ttMrtt
te'ttrrttgtgtttpB$t'tgttttte '---
tutu: ttra-ca-g:,':"-'::,:::::',,',',-:,:-:,',-,::):::]""
ml'll‘" 'AIALLIL “VI VII",
tgg w L
... srn.u-
m iiiir-1 L r
It's: a u u u n ale. .m'o, m
Figure 2. Timing Diagram (Binary Code 110101011001)
BINARY CODING
The A0572 binary output number N,, " B. B, B, . ' ' BI, is
related to the analog input voltage Em for all unipohr ranges by
the expression:
31211+Bzzl°+ mt'... +Ba20 Ere
211 = m
. . .whete B, = MSB, 8,, = LSB, and FSR = full-scale range.
For all bipolar ranges a fixed bipolar offset equal to L2“ is
internally summed with Em so that the sum of Em plus this
othet will be positive over the med operating range. For bipo-
lar ranges, expression (1) becomes:
B,2" +B,2'°+B,2'+ ...+Bl,2° m + T
tu = mr- (2)
Expressions (1) and (2) can be put in an alternate form:
(i''-+il'-Br'-da)ssRc=Em (3)
Unipolar (Binary Coding)
. . end .
fr'z''-+i'r'-ga)rsR-'-'f-'-aasm (4)
Bipolar (Offset Binary Coding)
Several examples will illustrate how this binary coding works.
0 TO +10 v INPUT RANGE
Assume FSR = to v end lh B, B, . Ah, - 110001000001,
then from (3), tim = " v +2.5 v +0.58 V + 0.0024V '*
+7.sss7 v.
-S V T0 +5 V INPUT RANGE
Assume FSR = 10 V " above, but that the bipolar offset is
connected and B, B, B, . .Bu '" 0110000000001. Then from
(4), Em = (+2.5 V + 1.25 V + 0.0024 V) - 5 v = -l.2476 V.
.-10 V TO +10 V INPUT RANGE
Assume the bipolar offset is connected as above, but that the
input span is now 20 V. Assuming the same digital output code
as in the -S V to +5 V input range example, from (4), Em -
(+5 V +2.5 ll +0.0049 V) -10 V = -2.495IV, or twice the
value of the previous example (neglecting round-off errors).
The encoding process defined by the previous relations (1) and
(2) or (3) and (4) determines that the analog input lies within
one of the 2" aa" 4096 quantization levels between i) and FSR
(or -FSR/2 end +FSRIZ). Figures 3 (A) end 3 (B) show the
actual device transfer curves for unipolar and bipolar ranges
(offset binary coding). They also show the ideal straight-line
transfer curves which pass through the center of each quantiza-
tion level. As can be seen from these figures, the actual and
ideal transfer curves differ by exactly t 1/2 LSB at the end of
each quantization interval, giving rise to the fundamental
21/2 LSB quantization error inherent in the digitizing process
"lt -u9
Dal "Mar" MVE
MUM. TRANS“. MVE
whisk "rs'
IDEAL YRAMSFEI CURVE
QCYUAL Y!M“ER CURVi
(8) Bipolar Range {Offset Binary Coding)
Figure 3. Unipolar and Bipolar Range Transfer Curves
ANALOG INPUT AND POWER CONNECTIONS
Offset Adjust: Analog and power connections for 0 to +10 V
unipolar and -10 V to +10 V bipolar input ranges are shown
in Figure 4 and 5, respectively. Bipolar Offset (Pin 23) is open-
circuited for All unipolu input ranges, and connected to Com.
parator Input (Pin 22) for all bipolar input ranges. The mo
adjust circuit consists of e potentiometer connected across tVs
with its slider connected through a 3.9 Mn resistor to Compare
tor Input (Pin 22) for all ranges. The tolerance of this fixed
resistor is not critical, and a carbon composition type is genet-
ally adequate. Using 3 carbon composition resistor having a
-1200 ppm/T tempco contribute: n wont-ase offset drift of
g x 244 x ltr' n x 1200 pmeC = 2.3 pmeC of FSR, ifthe
OFFSET AW potentiometer is set at either end of its adiust-
men: mge. Since the maximum offset adjustment required is
typically no more than t4 LSB, use of a carbon composition
offset summing resistor typically contributes no more than
1 ppmfC of FSR offset drift.
-4-. REV. A
anLoc DEUICES an-on-ntnnun Homut - Page 7
Digital Output Code
Analog Input - Volts Input Normalized (Binary for Unipolar Ranges;
(Center of ourttimtiort Interval) to FSR Ofhet Binary for Bipolar Ranges)
0 to +10 ht -S It to +5 V -10 V to +10 V Unipolu Bipolar BI Bi
mm Ram Range Rinses Ruse: (MSB) (LSB)
+9.99% 14.9976 +9.9951 +FSR-1 LSB +1/zFSR-1LSB 1 I 1 1 1 1 1 1 1 1 1 1
+9.9952 +4.9952 +9.9902 +FSR-ZLSB +1/2 st-z LSB 1 I 1 1 l 1 1 1 1 1 1 0
FS.0024 +0.00% +0.0049 +l/2 FSR+1 LSB +1 LSB 1 0 0 0 0 tl 0 0 0 0 0 l
+5.0000 1-0.0000 +0.0000 til FSR ZERO l 0 0 0 0 O 0 0 0 0 0 0
+0.0024 -4.9976 -9.9951 +1 LSB -112 FSRH LSB 0 0 0 0 0 " 0 0 0 0 0 l
+0.0000 -5.0000 -10.0000 ZERO -1/2 FSR t) 0 0 Ill. 0 0 i) 0 ll o 0
RANGE AND BUFFER FOLLOWER PIN CONNECTIONS
Analog pin connections for each of the ma, with and without
the buffer follower being used, are shown in Table II.
(“mam Cum
W Analog Canon Bipolar
1m. Followu- 'artrttort'm Spu Na: Hal! to:
Uled 30,and 29m 24
ttto +SV 15(022 -
Not Used "
Used 30.nd20uo24
" +lOV _ -
Not Uted " _
Used 30.and29to24
-M It to +2.5 V " to 22
Nor Used "
Used 30.nnd29t024
-5Vto+5 v - lt
Not Used "
Used 30.nd29w25
-10Vm+10V -
Not Used 15
Table II. Range and Buffer Follower Pin Connections
Wheutheanalogsigtulstturrehasalowimpedutceosmruld
be the case if it were the output of the sample-hold unpr1fier of
Figure 8), it can be connected to either of the direct input pins
24 and M. The buffer follower is used in the application as
sltttmtittFigure6,insdtichtttomlogiapttttothecotmrrer
comes directly from the output of I FET analog multiplexer.
Theseleeeddunnelhasatypitalr.,, = 2000whichhesa
3000 ppmPC tempco. If the multiplexer output were connected
to the 0 to +10 V direct input Pin 24 (S k0 input impedance,
nominal), this rm would introduce a 4% pin soledaetur load-
ing arm, which is well beyond the normal 20.25% FSR exter-
ml pin adjustment range. and a tempco of appmximately
3000 13me x 4% " 120 pmeC. By connecting the buffer
between the multiplexer output and direct input, these mm:
are eliminated. The buffer amplifier input bias current (50 nA
typical) must flow through the analog signal source, however.
This limits the upper pnetical source impedance to several kil-
ohma so that the offset voltage 1.”; Rwuxa an be kept
negligible, even though the buffer "tph'fier dynamic input im-
pedancez 100Mn.Thetmiferarnp1itierus_ttlittg
t.. am "
'ttr-w t ., , MIMI
'ttr- "
"ir""-"'"
T G "., . '
steam l: Cl) J -
enuMItMttR
AN" tir
Figure 7. Using Buffer Follower with Multiplexed Analog
time to 0.01% FSR for a 20 V input step. This must be added
to the conversion time when the input voltage can change signif-
icantly between successive conversions (as could be the case in
the circuit of Figure 7).
Short Cycie Input: A Short Cycle input (Pin 14) permits the
timing cycle shown in Figure 2 to be terminated after any num-
ber of desired bits have been converted, permitting somewhat
shorter conversion times in applications not requiring full 12-bit
resolution. When 12-bit resolution is required, Pin 14 is con-
nected to +5 V (Pin 16). When 10-bit resolution is desired, Pin
14 it connected to Bit 11 output Pin 2. The conversion cycle
then terminates, and the STATUS flag resets after the Bit to
decision (tn, +100 115 in timing diagram of Figure 2). Short cy-
cle pin connections and associated maximum w, 10- and 8-bit
conversion times are summarized in Table III.
Connect Short Maximum Status Fla;
Cycle Pin 14 to Resolution Conversion Reset at:
Pin: Bits (% FSR) Time (us) (Figure 2)
16 12 0.024 25 t12 + 100 ns
2 10 0.10 21 tm + 100 ns
4 8 0.39 17 t, + 100 ns
Table tll. Short Crete Connections
(One should note that the calibration voltages listed in Table I
are for 12-bit resolution only, and are those corresponding to the
center of each discrete quantization interval at reduced bit
resolutions.)
-tr- REV. A
