AD570SD ,Complete 8-Bit A-to-D ConverterFEATURESComplete A/D Converter with Reference and ClockFast Successive Approximation Conversion: 25 ..
AD571JD ,10-Bit A/D ConverterSpecifications subject to change without notice.
AD571KD ,10-Bit A/D ConverterSPECIFICATIONSAD571J AD571K AD571SModel Min Typ Max Min Typ Max Min Typ Max UnitsRESOLUTION 10 10 1 ..
AD571KD. ,10-Bit A/D ConverterSpecifications shown in boldface are tested on all production units at final electrical test. Resul ..
AD571KD+ ,10-Bit A/D ConverterSPECIFICATIONSAD571J AD571K AD571SModel Min Typ Max Min Typ Max Min Typ Max UnitsRESOLUTION 10 10 1 ..
AD571SD ,10-Bit A/D Converterspecifications are guaranteed, although only those shown in boldface are tested on all production u ..
AD9761ARS ,Dual 10-Bit TxDAC+⑩ with 2x Interpolation FiltersSPECIFICATIONS MIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 10 Bits1DC ACCURACYIntegral Linea ..
AD9761ARSRL ,10-Bit, Complete, 40 MSPS, dual Transmit D/A ConverterSPECIFICATIONSMIN Max OUTFSParameter Min Typ Max UnitRESOLUTION 10 Bits1DC ACCURACY Integral Nonl ..
AD9761ARSZ ,10-Bit, Complete, 40 MSPS, dual Transmit D/A ConverterSPECIFICATIONS50 Doubly Terminated, unless otherwise noted.)Parameter ..
AD9762AR ,12-Bit, 125 MSPS TxDAC D/A ConverterSPECIFICATIONSMIN MAX OUTFS Parameter Min Typ Max UnitsRESOLUTION 12 Bits1DC ACCURACYIntegral Linea ..
AD9763AST ,10-Bit, 125 MSPS Dual TxDAC+ D/A Converterapplications. The digital interface consists oftwo double-buffered latches as well as control logic ..
AD9763AST ,10-Bit, 125 MSPS Dual TxDAC+ D/A ConverterSPECIFICATIONSMIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 10 Bits1DC ACCURACYIntegral Linear ..
AD570JD-AD570SD
Complete 8-Bit A-to-D Converter
FUNCTIONAL BLOCK DIAGRAMComplete 8-Bit
A-to-D Converter
FEATURES
Complete A/D Converter with Reference and Clock
Fast Successive Approximation Conversion:25 ms
No Missing Codes Over Temperature
08C to +708C:AD570J
–558C to +1258C:AD570S
Digital Multiplexing:Three-State Outputs
18-Pin Ceramic DIP
Low Cost Monolithic Construction
PRODUCT DESCRIPTIONThe AD570 is an 8-bit successive approximation A/D converter
consisting of a DAC, voltage reference, clock, comparator, suc-
cessive approximation register and output buffers—all fabricated
on a single chip. No external components are required to per-
form a full accuracy 8-bit conversion in 25 μs.
The AD570 incorporates the most advanced integrated circuit
design and processing technology available today. I2L (inte-
grated injection logic) processing in the fabrication of the SAR
function along with laser trimming of the high stability SiCr
thin-film resistor ladder network at the wafer stage (LWT) and a
temperature compensated, subsurface Zener reference insures
full 8-bit accuracy at low cost.
Operating on supplies of +5 V and –15 V, the AD570 accepts
analog inputs of 0 V to +10 V unipolar of ±5 V bipolar, exter-
nally selectable. As the BLANK and CONVERT input is driven
low, the three-state outputs go into the high impedance state
and a conversion commences. Upon completion of the conver-
sion, the DATA READY line goes low and the data appears at
the output. Pulling the BLANK and CONVERT input high
three states the outputs and readies the device for the next con-
version. The AD570 executes a true 8-bit conversion with no
missing codes in approximately 25 μs.
The AD570 is available in two version; the AD570J is specified
for the 0°C to +70°C temperature range, the AD570S for –55°C
to +125°C. Both guarantee full 8-bit accuracy and no missing
codes over their respective temperature ranges.
*U.S. Patents Numbered:3,940,760; 4,213,806 and 4,136,349.REV.A
PRODUCT HIGHLIGHTSThe AD570 is a complete 8-bit A/D converter. No external
components are required to perform a conversion. Full-scale
calibration accuracy of ±0.8% (2 LSB of 8 bits) is achieved
without external trims.The AD570 is a single chip device employing the most ad-
vanced IC processing techniques. Thus, the user has at his
disposal a truly precision component with the reliability and
low cost inherent in monolithic construction,The AD570 accepts either unipolar (0 V to +10 V) or bipolar
(–5 V to +5 V) analog inputs by grounding or opening a
single pin.The device offers true 8-bit accuracy and exhibits no missing
codes over its entire operating temperature range.Operation is guaranteed with –15 V and +5 V supplies. The
device will also operate with a –12 V supply.The AD570S is also available processed to MIL-STD-883C,
Class B. The military data sheet for the AD570SD/883B is
included in the Analog Devices Military Products Databook.
AD570–SPECIFICATIONS
(TA = +258C, V+ = +5 V, V– = –12 V or –15 V, all voltages measured with respect to
digital common, unless otherwise noted)NOTESThe AD570 is a selected version of the AD571 10-bit A-to-D converter. Only TTL logic inputs should be connected to Pins 1 and 18 (or no connection made) or
damage may result.For details on grade package offerings for SD-grade in accorance with MIL-STD-883, refer to Analog Devices’ Military Products databook or current /883 data sheet.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
signal, an input current will be generated which exactly matches
the DAC output with all bits on. (The input resistor is trimmed
slightly low to facilitate user trimming, as discussed on the next
page.)
POWER SUPPLY SELECTIONThe AD570 is designed and specified for optimum performance
using a +5 V and –15 V supply. The supply current drawn by
the device is a function of the operating mode (BLANK or
CONVERT), as given on the specification page. The supply
currents change only moderately over temperature as shown in
Figure 2, and do not change significantly with changes in V–
from –10.8 volts to –16 volts.
Figure 2.AD570 Power Supply Current vs. Temperature
CONNECTING THE AD570 FOR STANDARD
OPERATIONThe AD570 contains all the active components required to per-
form a complete A/D conversion. Thus, for most situations, all
that is necessary is to connect the power supply (+5 V and –15 V),
the analog input, and the conversion start signal. But, there are
some features and special connections which should be consid-
ered for achieving optimum performance. The functional pinout
is shown in Figure 3.
ABSOLUTE MAXIMUM RATINGSV+ to Digital Common . . . . . . . . . . . . . . . . . . . . .0 V to +7 V
V– to Digital Common . . . . . . . . . . . . . . . . . .0 V to –16.5 V
Analog Common to Digital Common . . . . . . . . . . . . . . .±1 V
Analog Input to Analog Common . . . . . . . . . . . . . . . . .±15 V
Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to V+
Digital Outputs (Blank Mode) . . . . . . . . . . . . . . . . . .0 V to V+
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .800 mW
CIRCUIT DESCRIPTIONThe AD570 is a complete 8-bit A/D converter which requires
no external components to provide the complete successive-
approximation analog-to-digital conversion function. A block
diagram of the AD570 is shown on last page. Upon receipt of
the CONVERT command, the internal 8-bit current output
DAC is sequenced by the I2L successive-approximation register
(SAR) from its most-significant bit (MSB) to least-significant
bit (LSB) to provide an output current which accurately bal-
ances the input signal current through the 5 kΩ input resistor.
The comparator determines whether the addition of each suc-
cessively-weighted bit current causes the DAC current sum to
be greater or less than the input current; if the sum is less the bit
is left on, if more, the bit is turned off. After testing all the bits,
the SAR contains a 8-bit binary code which accurately repre-
sents the input signal to within ±1/2 LSB (0.20%).
Upon completion of the sequence, the DATA READY signal
goes low, and the bit output lines become active high or low
depending on the code in the SAR. When the BLANK and
CONVERT line is brought high, the output buffers again go
“open”, and the SAR is prepared for another conversion cycle.
The temperature compensated buried Zener reference provides
the primary voltage reference to the DAC and guarantees excel-
lent stability with both time and temperature. The bipolar offset
input controls a switch which allows the positive bipolar offset
current (exactly equal to the value of the MSB less 1/2 LSB)
0.120Figure 1.Chip Bonding Diagram
AD570
FULL-SCALE CALIBRATIONThe 5 kΩ thin-film input resistor is laser trimmed to produce a
current which matches the full-scale current of the internal
DAC—plus about 0.3%—when a full-scale analog input voltage
of 9.961 volts (10 volts—1 LSB) is applied at the input. The in-
put resistor is trimmed in this way so that if a fine trimming
potentiometer is inserted in series with the input signal, the in-
put current at the full-scale input voltage can be trimmed down
to match the DAC full-scale current as precisely as desired.
However, for many applications the nominal 9.961 volt full
scale can be achieved to sufficient accuracy by simply inserting a
15 Ω resistor in series with the analog input to Pin 13. Typical
full-scale calibration error will then be about ±2 LSB or ±0.8%.
If a more precise calibration is desired, a 200 Ω trimmer should
be used instead. Set the analog input at 9.961 volts, and set the
trimmer so that the output code is just at the transition between
11111110 and 11111111. Each LSB will then have a weight of
39.06 mV. If a nominal full scale of 10.24 volts is desired
(which makes the LSB have a value of exactly 40.00 mV), a
50 Ω resistor in series with a 200 Ω trimmer (or a 500 Ω trim-
mer with good resolution) should be used. Of course, larger full-
scale ranges can be arranged by using a larger input resistor, but
linearity and full-scale temperature coefficient may be compro-
mised if the external resistor becomes a sizable percentage of
5 kΩ.
BIPOLAR OPERATIONThe standard unipolar 0 V to +10 V range is obtained by short-
ing the bipolar offset control pin to digital common. If the pin is
left open, the bipolar offset current will be switched into the
comparator summing node, giving a –5 V to +5 V range with an
Figure 4.Standard AD570 Connections
offset binary output code. (–5.00 volts in will give a 8-bit code
of 00000000; an input of 0.00 volts results in an output code of
10000000 and 4.96 volts at the input yields the 11111111 code.)
The bipolar offset control input is not directly TTL compatible,
but a TTL interface for logic control can be constructed as
shown in Figure 5.
Figure 5.Bipolar Offset Controlled by Logic Gate
Gate Output = 1: Unipolar 0 V–10 V Input Range
Gate Output = 0: Bipolar ±5 V Input Range
COMMON-MODE RANGEThe AD570 provides separate analog and digital common con-
nections. The circuit will operate properly with as much as
±200 mV of common-mode range between the two commons.
This permits more flexible control of system common bussing
and digital and analog returns.
In normal operation the analog common terminal may generate
transient currents of up to 2 mA during a conversion. In addi-
tion, a static current of about 2 mA will flow into analog com-
mon in the unipolar mode after a conversion is complete. An
additional 1 mA will flow in during a blank interval with zero
analog input. The analog common current will be modulated by
the variations in input signal.
The absolute maximum differential voltage rating between the
two commons is ±1 volt. We recommend that a parallel pair of
back-to-back protection diodes can be connected as shown in
Figure 6 if they are not connected locally.
Figure 6.Differential Common Voltage Protection
ZERO OFFSETThe apparent zero point of the AD570 can be adjusted by in-
serting an offset voltage between the analog common of the de-
vice and the actual signal return or signal common. Figure 7
illustrates two methods of providing this offset. Figure 7a shows
how the converter zero may be offset by up to ±3 bits to correct
the device initial offset and/or input signal offsets. As shown, the
circuit gives approximately symmetrical adjustment in unipolar
mode. In bipolar mode R2 should be omitted to obtain a sym-
metrical range.
Figure 7a.
Figure 7b.
Figure 8 shows the nominal transfer curve near zero for an
AD570 in unipolar mode. The code transitions are at the edges
of the nominal bit weights. In some applications it will be pref-
erable to offset the code transitions so that they fall between the
nominal bit weights, as shown in the offset characteristics. This
offset can easily be accomplished as shown in Figure 7b.
At balance (after a conversion) approximately 2 mA flows into
the analog common terminal. A 10 Ω resistor in series with this
terminal will result in approximately the desired 1/2 bit offset of
the transfer characteristics. The nominal 2 mA analog common
current is not closely controlled in manufacture. If high accuracy
is required, a 20 Ω potentiometer (connected as a rheostat) can
be used as R1. Additional negative offset range may be obtained
by using larger values of R1. Of course, if the zero transition
point is changed, the full-scale transition point will also move.
Thus, if an offset of 1/2 LSB is introduced, full-scale trimming
as described on previous page should be done with an analog
input of 9.941 volts.
Figure 8.AD570 Transfer Curve—Unipolar Operation
(Approximate Bit Weights Shown for Illustration, Nominal
Bit Weights , 36.1 mV)
NOTE: During a conversion transient currents from the analog
common terminal will disturb the offset voltage. Capacitive de-
coupling should not be used around the offset network. These
transients will settle as appropriate during a conversion. Capaci-
tive decoupling will “pump up” and fail to settle resulting in
conversion errors. Power supply decoupling which returns to
analog signal common should go to the signal input side of the
resistive offset network.
CONTROL AND TIMING OF THE AD570There are several important timing and control features on the
AD570 which must be understood precisely to allow optimal
interfacing to microprocessor or other types of control systems.
All of these features are shown in the timing diagram in Figure 9.
The normal standby situation is shown at the left end of the
drawing. The BLANK and CONVERT (B & C) line is held
high, the output lines will be “open”, and the DATA READY
(DR) line will be high. This mode is the lowest power state of
the device (typically 150 mW). When the (B & C ) line is
brought low, the conversion cycle is initiated; but the DR and
data lines do not change state. When the conversion cycle is
complete (typically 25 μs), the DR line goes low, and within
500 ns, the data lines become active with the new data.
About 1.5 μs after the B & C line is again brought high, the DR
line will go high and the data lines will go open. When the
B & C line is again brought low, a new conversion will begin.
AD570the DR and data lines will not change. If a 2 μs or longer pulse
is applied to the B & C line during a conversion, the converter
will clear and start a new conversion cycle.
Figure 9.AD570 Timing and Control Sequence
CONTROL MODES WITH BLANK AND CONVERTThe timing sequence of the AD570 discussed above allows the
device to be easily operated in a variety of systems with differing
control modes. The two most common control modes, the Con-
vert Pulse Mode, and the Multiplex Mode, are illustrated here.
Convert Pulse Mode–In this mode, data is present at the output
of the converter at all times except when conversion is taking
place. Figure 10 illustrates the timing of this mode. The BLANK
and CONVERT line is normally low and conversions are trig-
gered by a positive pulse. A typical application for this timing
mode is shown in Figure 13, in which μP bus interfacing is
easily accomplished with three-state buffers.
Multiplex Mode—In this mode the outputs are blanked except
when the device is selected for conversion and readout; this tim-
ing is shown in Figure 11. A typical AD570 multiplexing appli-
cation is shown in Figure 14.
This operating mode allows multiple AD570 devices to drive
common data lines. All BLANK and CONVERT lines are held
high to keep the outputs blanked. A single AD570 is selected, its
BLANK and CONVERT line is driven low and at the end of
conversion, which is indicated by DATA READY going low, the
conversion result will be present at the outputs. When this data
has been read from the 8-bit bus, BLANK and CONVERT is
restored to the blank mode to clear the data bus for other con-
verters. When several AD570s are multiplexed in sequence, a
new conversion may be started in one AD570 while data is
being read from another. As long as the data is read and the first
AD570 is cleared within 15 μs after the start of conversion of the
second AD570, no data overlap will occur.
Figure 11.Multiplex Mode
SAMPLE-HOLD AMPLIFIER CONNECTION TO THE
AD570Many situations in high-speed acquisition systems or digitizing
of rapidly changing signals require a sample-hold amplifier
(SHA) in front of the A-D converter. The SHA can acquire and
hold a signal faster than the converter can perform a conversion.
A SHA can also be used to accurately define the exact point in
time at which the signal is sampled. For the AD570, a SHA can
also serve as a high input impedance buffer.
Figure 12 shows the AD570 connected to the AD582 mono-
lithic SHA for high speed signal acquisition. In this configura-
tion, the AD582 will acquire a 10 volt signal in less than 10 μs
with a droop rate less than 100 μV/ms. The control signals are
arranged so that when the control line goes low, the AD582 is put
into the “hold” mode, and the AD570 will begin its conversion
cycle. (The AD582 settles to final value well in advance of the
Figure 12.Sample-Hold Interface to the AD570
first comparator decision inside the AD570). The DATA
READY line is fed back to the other side of the differential
input control gate so that the AD582 cannot come out of the
“hold” mode during the conversion cycle. At the end of the con-
version cycle, the DATA READY line goes low, automatically
placing the AD582 back into the sample mode. This feature al-
lows simple control of both the SHA and the A-D converter
with a single line. Observe carefully the ground, supply, and by-
pass capacitor connections between the two devices. The ar-
rangement minimizes ground noise and interference during the
conversion cycle to give the most accurate measurements.
