AD569BD ,16-Bit Monotonic Voltage Output D/A Converterapplications.wiring resistances and ground currents.Data may be loaded into the AD569’s input latch ..
AD569JN ,16-Bit Monotonic Voltage Output D/A Converterspecifications.CMOS-compatible signals control the latches: CS, LBE, HBE,and LDACThe AD569 is avail ..
AD569JP ,16-Bit Monotonic Voltage Output D/A ConverterCHARACTERISTICSVoltage –5 +5 –5 +5 –5 +5 VoltsCapacitive Load 1000 1000 1000 pFResistive Load 1 1 1 ..
AD569KN ,16-Bit Monotonic Voltage Output D/A ConverterCHARACTERISTICSVoltage –5 +5 –5 +5 –5 +5 VoltsCapacitive Load 1000 1000 1000 pFResistive Load 1 1 1 ..
AD569KP ,16-Bit Monotonic Voltage Output D/A ConverterSPECIFICATIONS otherwise noted.)Model AD569JN/JP/AD AD569KN/KP/BD AD569SDParam ..
AD570JD ,Complete 8-Bit A-to-D ConverterSPECIFICATIONSAD570J AD570SModel Min Typ Max Min Typ Max Units1RESOLUTION 8 8 BitsRELATIVE ACCURACY ..
AD9754ARU ,14-Bit, 125 MSPS High Performance TxDAC D/A Converterapplications. Matching between the twoDirect IFcurrent outputs ensures enhanced dynamic performance ..
AD9754AR-U ,14-Bit, 125 MSPS High Performance TxDAC D/A Converterapplications. Its power dissipation can be further reduc-component selection path based on resoluti ..
AD9755AST ,12-Bit, 300 MSPS High-Speed TxDAC+?? D/A ConverterSPECIFICATIONSDifferential Transformer Coupled Output, 50 Doubly Terminated, unless otherwise not ..
AD9760AR ,10-Bit, 125 MSPS TxDAC D/A ConverterSPECIFICATIONSMIN MAX OUTFS Parameter Min Typ Max UnitsRESOLUTION 10 Bits1DC ACCURACYIntegral Linea ..
AD9760AR50 ,10-Bit, 125 MSPS TxDAC D/A Converterapplications. Matching between the twoInstrumentationcurrent outputs ensures enhanced dynamic perfo ..
AD9760AR50 ,10-Bit, 125 MSPS TxDAC D/A ConverterFEATURES Member of Pin-Compatible TxDAC Product Family+5V125 MSPS Update Rate 0.1F10-Bit Resolutio ..
AD569AD-AD569BD-AD569JN-AD569JP-AD569KN-AD569KP
16-Bit Monotonic Voltage Output D/A Converter
FUNCTIONAL BLOCK DIAGRAMREV.A
16-Bit Monotonic
Voltage Output D/A Converter
FEATURES
Guaranteed 16-Bit Monotonicity
Monolithic BiMOS II Construction60.01% Typical Nonlinearity
8- and 16-Bit Bus Compatibility
3 ms Settling to 16 Bits
Low Drift
Low Power
Low Noise
APPLICATIONS
Robotics
Closed-Loop Positioning
High-Resolution ADCs
Microprocessor-Based Process Control
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTIONThe AD569 is a monolithic 16-bit digital-to-analog converter
(DAC) manufactured in Analog Devices’ BiMOS II process.
BiMOS II allows the fabrication of low power CMOS logic
functions on the same chip as high precision bipolar linear cir-
cuitry. The AD569 chip includes two resistor strings, selector
switches decoding logic, buffer amplifiers, and double-buffered
input latches.
The AD569’s voltage-segmented architecture insures 16-bit
monotonicity over time and temperature. Integral nonlinearity is
maintained at ±0.01%, while differential nonlinearity is0.0004%. The on-chip, high-speed buffer amplifiers provide a
voltage output settling time of 3 μs to within ±0.001% for a
full-scale step.
The reference input voltage which determines the output range
can be either unipolar or bipolar. Nominal reference range is5 V and separate reference force and sense connections are
provided for high accuracy applications. The AD569 can oper-
ate with an ac reference in multiplying applications.
Data may be loaded into the AD569’s input latches from 8- and
16-bit buses. The double-buffered structure simplifies 8-bit bus
interfacing and allows multiple DACs to be loaded asynchro-
nously and updated simultaneously. Four TTL/LSTTL/5 V
CMOS-compatible signals control the latches: CS, LBE, HBE,
and LDAC
The AD569 is available in five grades: J and K versions are
specified from 0°C to +70°C and are packaged in a 28-pin plas-
tic DIP and 28-pin PLCC package; AD and BD versions are
specified from –25°C to +85°C and are packaged in a 28-pin
ceramic DIP. The SD version, also in a 28-pin ceramic DIP, is
specified from –55°C to +125°C.
PRODUCT HIGHLIGHTS1. Monotonicity to 16 bits is insured by the AD569’s voltage-
segmented architecture.
2. The output range is ratiometric to an external reference or ac
signal. Gain error and gain drift of the AD569 are negligible.
3. The AD569’s versatile data input structure allows loading
from 8- and 16-bit buses.
4. The on-chip output buffer amplifier can supply ±5 V into a
1 kΩ load, and can drive capacitive loads of up to 1000 pF.
5. Kelvin connections to the reference inputs preserve the gain
and offset accuracy of the transfer function in the presence of
wiring resistances and ground currents.
6. The AD569 is available in versions compliant with MIL-STD-
883. Refer to the Analog Devices Military Products Data-
book or current AD569/883B data sheet for detailed
specifications.
AD569–SPECIFICATIONSREFERENCE INPUT
NOTESFSR stands for Full-Scale Range, and is 10 V for a –5 V to +5 V span.Refer to Definitions section.For operation with supplies other than ±12 V, refer to the Power Supply and Reference Voltage Range Section.Measured between +VREF Force and –VREF Force.Sensitivity of Full-Scale Error due to changes in +VS and sensitivity of Offset to changes in –VS.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
(TA = +258C, +VS = +12 V, –VS = –12 V, +VREF = +5 V, –VREF = –5 V, unless
otherwise noted.)
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance Only and are not subject to test.
+VS = +12 V; –VS = –12 V; +VREF = +5 V; –VREF = –5 V excepts where stated.Output Noise Voltage
TIMING CHARACTERISTICS(+VS = +12 V, –VS = –12 V, VIH = 2.4 V, VIL = 0.4 V,TMIN to TMAX)tWC
tSC
tHC
Case B
tWB
tHCS
tWD
Case C
tWB
Figure 2b. AD569 Timing Diagram – Case CFigure 1. AD569 Timing Diagram – Case A
AD569
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
+VS (Pin 1) to GND (Pin 18) . . . . . . . . . . . . . .+18 V, –0.3 V
–VS (Pin 28) to GND (Pin 18) . . . . . . . . . . . . . .–18 V, +0.3 V
+VS (Pin 1) to –VS (Pin 28) . . . . . . . . . . . . . . .+26.4 V, –0.3 V
Digital Inputs
(Pins 4-14, 19-27) to GND (Pin 18) . . . . . . . . .+VS, –0.3 V
+VREF Force (Pin 3) to +VREF Sense (Pin 2) . . . . . . . .±16.5 V
–VREF Force (Pin 15) to –VREF Sense (Pin 16) . . . . . . .±16.5 V
VREF Force (Pins 3, 15) to GND (Pin 18) . . . . . . . . . . . . .±VS
VREF Sense (Pins 2, 16) to GND (Pin 18) . . . . . . . . . . . . .±VS
VOUT (Pin 17) . . . . . . . . . . . . . . . . . .Indefinite Short to GND
. . . . . . . . . . . . . . . . . . . . . . . .Momentary Short to +VS, –VS
Power Dissipation (Any Package) . . . . . . . . . . . . . . .1000 mW
Operating Temperature Range
Commercial Plastic (JN, KN, JP, KP Versions)0°C to +70°C
Industrial Ceramic (AD, BD Versions) . . . .–25°C to +85°C
Extended Ceramic (SD Versions) . . . . . . .–55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range (Soldering, 10 secs) . . . . . . .+300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITYThe AD569 features input protection circuitry consisting of large “distributed” diodes and polysilicon
series resistors to dissipate both high-energy discharges (Human Body Model) and fast, low-energy
pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD569 has been
classified as a Category A device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment
and discharge without detection. Unused devices must be stored in conductive foam or shunts, and
the foam should be discharged to the destination socket before devices are removed. For further
information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.
PIN DESIGNATIONS
ORDERING GUIDE
Figure 3. AD569 Block Diagram
FUNCTIONAL DESCRIPTIONThe AD569 consists of two resistor strings, each of which is di-
vided into 256 equal segments (see Figure 3). The 8 MSBs of
the digital input word select one of the 256 segments on the first
string. The taps at the top and bottom of the selected segment
are connected to the inputs of the two buffer amplifiers A1 and
A2. These amplifiers exhibit extremely high CMRR and low
bias current, and thus accurately preserve the voltages at the top
and bottom of the segment. The buffered voltages from the seg-
ment endpoints are applied across the second resistor string,
where the 8LSBs of the digital input word select one of the 256
taps. Output amplifier A3 buffers this voltage and delivers it to
the output.
Buffer amplifiers A1 and A2 leap-frog up the first string to pre-
serve monotonicity at the segment boundaries. For example,
when increasing the digital code from 00FFH to 0100H, (the first
segment boundary), A1 remains connected to the same tap on
the first resistor, while A2 jumps over it and is connected to the
tap which becomes the top of the next segment. This design
guarantees monotonicity even if the amplifiers have offset volt-
ages. In fact, amplifier offset only contributes to integral linear-
ity error.
CAUTIONIt is generally considered good engineering practice to avoid
inserting integrated circuits into powered-up sockets. This
guideline is especially important with the AD569. An empty,
powered-up socket configures external buffer amplifiers in an
open-loop mode, forcing their outputs to be at the positive or
negative rail. This condition may result in a large current surge
between the reference force and sense terminals. This current
surge may permanently damage the AD569.
ANALOG CIRCUIT DETAILSMONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs. All
versions of the AD569 are monotonic over their full operating
temperature range.
DIFFERENTIAL NONLINEARITY: DNL is the measure of
the change in the analog output, normalized to full scale, associ-
ated: with a 1 LSB change in the digital input code. Monotonic
behavior requires that the differential linearity error be less than
1 LSB over the temperature range of interest. For example, for a
±5 V output range, a change of 1 LSB in digital input code
should result in a 152 μV change in the analog output (1 LSB =
10 V/65,536). If the change is actually 38 μV, however, the dif-
ferential linearity error would be –114 μV, or –3/4 LSB. By leap-
frogging the buffer amplifier taps on the first divider, a typical
AD569 keeps DNL within ±38 μV (±1/4 LSB) around each of
the 256 segment boundaries defined by the upper byte of the in-
put word (see Figure 5). Within the second divider, DNL also
typically remains less than ±38 μV as shown in Figure 6. Since
the second divider is independent of absolute voltage, DNL is
the same within the rest of the 256 segments.
OFFSET ERROR: The difference between the actual analog
output and the ideal output (–VREF), with the inputs loaded with
all zeros is called the offset error. For the AD569, Unipolar Off-
set is specified with 0 V applied to –VREF and Bipolar Offset is
specified with –5 V applied to –VREF. Either offset is trimmed by
adjusting the voltage applied to the –VREF terminals.
BIPOLAR ZERO ERROR: The deviation of the analog output
DefinitionsLINEARITY ERROR: Analog Devices defines linearity error as
the maximum deviation of the actual, adjusted DAC output
from the ideal output (a straight line drawn from 0 to FS–1LSB)
for any bit combination. The AD569’s linearity is primarily lim-
ited by resistor uniformity in the first divider (upper byte of
16-bit input). The plot in Figure 4 shows the AD569’s typical
linearity error across the entire output range to be within0.01% of full scale. At 25°C the maximum linearity error for
the AD569JN, AD and SD grades is specified to be ±0.04%,
and ±0.024% for the KN and BD versions.
AD569Figure 5. Typical DNL at Segment Boundary Transitions
a. Segment 1
b. Segment 256
Figure 6. Typical DNL Within Segments
MULTIPLYING FEEDTHROUGH ERROR: This is the error
due to capacitive feedthrough from the reference to the output
with the input registers loaded with all zeroes.
FULL-SCALE ERROR: The AD569’s voltage dividing archi-
tecture gives rise to a fixed full-scale error which is independent
of the reference voltage. This error is trimmed by adjusting the
voltage applied to the +VREF terminals.
Glitches can be due to either time skews between the input bits
or charge injection from the internal switches. Glitch Impulse
for the AD569 is mainly due to charge injection, and is mea-
sured with the reference connections tied to ground. It is speci-
fied as the area of the glitch in nV-secs.
TOTAL ERROR: The worst-case Total Error is the sum of the
fixed full-scale and offset errors and the linearity error.
POWER SUPPLY AND REFERENCE VOLTAGE RANGESThe AD569 is specified for operation with ±12 volt power
supplies. With ±10% power supply tolerances, the maximum
reference voltage range is ±5 volts. Reference voltages up to
±6 volts can be used but linearity will degrade if the supplies
approach their lower limits of ±10.8 volts (12 volts - 10%).
If ±12 volt power supplies are unavailable in the system, several
alternative schemes may be used to obtain the needed supply
voltages. For example, in a system with ±15 V supplies, a single
Zener diode can be used to reduce one of the supplies to 9 volts
with the remaining one left at 15 volts. Figure 7a illustrates this
scheme. A 1N753A or equivalent diode is an appropriate choice
for the task. Asymmetrical power supplies can be used since the
AD569’s output is referenced to –VREF only and thus floats
relative to logic ground (GND, Pin 18). Assuming a worst-case
±1.5 volt tolerance on both supplies (10% of 15 volts), the
maximum reference voltage ranges would be +6 and –2 volts for
+VS = +15 V and VS = –9 V, and +2 to –8 volts for +VS = 9 V
and –VS = –15 V .
Alternately, two 3 V Zener diodes or voltage regulators can be
used to drop each ±15 volt supply to ±12 volts, respectively. In
Figure 7b, 1N746A diodes are a good choice for this task.
A third method may be used if both ±15 volt and ±5 volt sup-
plies are available. Figure 7c shows this approach. A combina-
tion of +VS = +15 V and –VS = –5 V can support a reference
range of 0 to 6 volts, while supplies of +VS = +5 V and –VS =
–15 V can support a reference range of 0 to –8 volts. Again,
10% power supply tolerances are assumed.
NOTE: Operation with +VS = +5 V alters the input latches’ op-
erating conditions causing minimum write pulse widths to ex-
tend to 1 μs or more. Control signals CS, HBE, LBE, and
LDAC should, therefore, be tied low to render the latches trans-
parent.
No timing problems exist with operation at +VS = 9 V and
–VS = –15 V. However, 10% tolerances on these supplies gener-
ate a worst-case condition at –VS = –16.5 V and +VS = +7.5 V
(assuming +VS is derived from a +15 V supply). Under these
conditions, write pulse widths can stretch to 200 ns with similar
degradation of data setup and hold times. However, ±0.75 V
tolerances (±5%) yield minimal effects on digital timing with
write pulse widths remaining below 100 ns.
Finally, Figure 7d illustrates the use of the combination of an
AD588 and AD569 in a system with ±15 volt supplies. As
shown, the AD588 is connected to provide ±5 V to the refer-
ence inputs of the AD569. It is doing double-duty by simulta-
neously regulating the supply voltages for the AD569 through
the use of the level shifting Zeners and transistors. This scheme
utilizes the capability of the outputs of the AD588 to source as
