AD568JQ ,12-Bit Ultrahigh Speed Monolithic D/A ConverterSpecifications subject to change without notice.–2– REV. AAD568LSB MSBPIN CONFIGURATION12 11 10 9 8 ..
AD568SQ ,12-Bit Ultrahigh Speed Monolithic D/A ConverterSPECIFICATIONSCC EEModel AD568J AD568K AD568SMin Typ Max Min Typ Max Min Typ Max UnitsRESOLUTION 12 ..
AD569AD ,16-Bit Monotonic Voltage Output D/A ConverterFEATURESGuaranteed 16-Bit MonotonicityMonolithic BiMOS II Construction60.01% Typical Nonlinearity8- ..
AD569BD ,16-Bit Monotonic Voltage Output D/A Converterapplications.wiring resistances and ground currents.Data may be loaded into the AD569’s input latch ..
AD569JN ,16-Bit Monotonic Voltage Output D/A Converterspecifications.CMOS-compatible signals control the latches: CS, LBE, HBE,and LDACThe AD569 is avail ..
AD569JP ,16-Bit Monotonic Voltage Output D/A ConverterCHARACTERISTICSVoltage –5 +5 –5 +5 –5 +5 VoltsCapacitive Load 1000 1000 1000 pFResistive Load 1 1 1 ..
AD9754 ,14-Bit, 100 MSPS+ TxDAC?D/A Converterapplications. Matching between the twoDirect IFcurrent outputs ensures enhanced dynamic performance ..
AD9754AR ,14-Bit, 125 MSPS High Performance TxDAC D/A ConverterSPECIFICATIONSParameter Min Typ Max UnitsDYNAMIC PERFORMANCEMaximum Output Update Rate (f ) 125 MSP ..
AD9754AR ,14-Bit, 125 MSPS High Performance TxDAC D/A ConverterSPECIFICATIONSMIN MAX OUTFS Parameter Min Typ Max UnitsRESOLUTION 14 Bits1DC ACCURACYIntegral Linea ..
AD9754ARU ,14-Bit, 125 MSPS High Performance TxDAC D/A ConverterFEATURES+5VHigh Performance Member of Pin-CompatibleTxDAC Product FamilyREFLO AVDDACOM150pF125 MSPS ..
AD9754ARU ,14-Bit, 125 MSPS High Performance TxDAC D/A Converterapplications. Matching between the twoDirect IFcurrent outputs ensures enhanced dynamic performance ..
AD9754AR-U ,14-Bit, 125 MSPS High Performance TxDAC D/A Converterapplications. Its power dissipation can be further reduc-component selection path based on resoluti ..
AD568JQ-AD568SQ
12-Bit Ultrahigh Speed Monolithic D/A Converter
FUNCTIONAL BLOCK DIAGRAMREV. A
12-Bit Ultrahigh Speed
Monolithic D/A Converter
FEATURES
Ultrahigh Speed: Current Settling to 1 LSB in 35 ns
High Stability Buried Zener Reference on Chip
Monotonicity Guaranteed Over Temperature
10.24 mA Full-Scale Output Suitable for Video
Applications
Integral and Differential Linearity Guaranteed Over
Temperature
0.3" “Skinny DIP” Packaging
Variable Threshold Allows TTL and CMOS
Interface
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTIONThe AD568 is an ultrahigh-speed, 12-bit digital-to-analog con-
verter (DAC) settling to 0.025% in 35 ns. The monolithic de-
vice is fabricated using Analog Devices’ Complementary Bipolar
(CB) Process. This is a proprietary process featuring high-speed
NPN and PNP devices on the same chip without the use of di-
electric isolation or multichip hybrid techniques. The high speed
of the AD568 is maintained by keeping impedance levels low
enough to minimize the effects of parasitic circuit capacitances.
The DAC consists of 16 current sources configured to deliver a
10.24 mA full-scale current. Multiple matched current sources
and thin-film ladder techniques are combined to produce bit
weighting. The DAC’s output is a 10.24 mA full scale (FS) for
current output applications or a 1.024 V FS unbuffered voltage
output. Additionally, a 10.24 V FS buffered output may be gen-
erated using an onboard 1 kΩ span resistor with an external op
amp. Bipolar ranges are accomplished by pin strapping.
Laser wafer trimming insures full 12-bit linearity. All grades of
the AD568 are guaranteed monotonic over their full operating
temperature range. Furthermore, the output resistance of the
DAC is trimmed to 100 Ω ± 1.0%. The gain temperature coeffi-
cient of the voltage output is 30 ppm/°C max (K).
The AD568 is available in three performance grades. The
AD568JQ and KQ are available in 24-pin cerdip (0.3") packages
and are specified for operation from 0°C to +70°C. The
AD568SQ features operation from –55°C to +125°C and is also
packaged in the hermetic 0.3" cerdip.
PRODUCT HIGHLIGHTSThe ultrafast settling time of the AD568 allows leading edge
performance in waveform generation, graphics display and
high speed A/D conversion applications.Pin strapping provides a variety of voltage and current output
ranges for application versatility. Tight control of the abso-
lute output current reduces trim requirements in externally-
scaled applications.Matched on-chip resistors can be used for precision scaling in
high speed A/D conversion circuits.The digital inputs are compatible with TTL and +5 V
CMOS logic families.Skinny DIP (0.3") packaging minimizes board space require-
ments and eases layout considerations.The AD568 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD568/883B data sheet for detailed
specifications.
DATA INPUTS
NOTES
*Same as AD568J.Measured in IOUT mode.
(@ = +258C, VCC, VEE = 615 V unless otherwise noted)AD568–SPECIFICATIONS
AD568their glitch impulse. It is specified as the net area of the glitch in
nV-sec or pA-sec.
COMPLIANCE VOLTAGE: The range of allowable voltage at
the output of a current-output DAC which will not degrade the
accuracy of the output current.
SETTLING TIME: The time required for the output to reach
and remain within a specified error band about its final value,
measured from the digital input transition.
TIME – ns
OUTPUT – VOLTS
0.4Figure 2.Glitch Impulse
Connecting the AD568
UNBUFFERED VOLTAGE OUTPUT
Unipolar ConfigurationFigure 3 shows the AD568 configured to provide a unipolar 0 to
+1.024 V output range. In this mode, the bipolar offset termi-
nal, Pin 21, should be grounded if not used for offset trimming.
The nominal output impedance of the AD568 with Pin 19
grounded has been trimmed to 100 Ω, ±1%. Other output im-
pedances can be generated with an external resistor, REXT, be-
tween Pins 19 and 20. An REXT equalling 300 Ω will yield a
total output resistance of 75 Ω, while an REXT of 100 Ω will pro-
vide 50 Ω of output resistance. Note that since the full-scale
output current of the DAC remains 10.24 mA, changing the
load impedance changes the unbuffered output voltage accord-
ingly. Settling time and full-scale range characteristics for these
load impedances are provided in the specifications table.
Bipolar ConfigurationFigure 4 shows the connection scheme used to provide a bipolar
output voltage range of 1.024 V. The bipolar offset (–0.512 V)
occurs when all bits are OFF (00 . . . 00), bipolar zero (0 V) oc-
curs when the MSB is ON with all other bits OFF (10 . . . 00),
and full-scale minus 1 LSB (0.51175 V) is generated when all
DIGITAL
INPUTS
–15V+15VDIGITAL
SUPPLY
GROUND
+5V
REXT
(OPTIONAL)
FERRITE BEADS
STACKPOLE 57-1392Figure 3.Unipolar Output Unbuffered 0 V to +1.024 V
Figure 4.Bipolar Output Unbuffered ±0.512 V
BIPOLAR ZERO ERROR: The deviation of the analog output
from the ideal half-scale output of 0 V (or 0 mA) for bipolar
mode when only the MSB is on (100 . . .00) is called bipolar
zero error.
GAIN ERROR: The difference between the ideal and actual
output span of FS –1 LSB, expressed in % of FS, or LSB, when
all bits are on.
GLITCH IMPULSE: Asymmetrical switching times in a DAC
give rise to undesired output transients which are quantified by
DIGITAL
INPUTS
–15V+15VDIGITAL
SUPPLY
GROUND
+5V
ANALOG
SUPPLY
GROUNDFigure 5.Bipolar Output Unbuffered ±1.024 V
Optional Gan and Zero AdjustmentThe gain and offset are laser trimmed to minimize their effects
on circuit performance. However, in some applications, it may
be desirable to externally reduce these errors further. In those
cases, the following procedures are suggested.
UNIPOLAR MODE: (Refer to Figure 6)
Step 1 – Set all bits (BIT 1–BIT 12) to Logic “0” (OFF)—note
the output voltage. This is the offset error.
Step 2 – Set all bits to Logic “1” (ON). Adjust the gain trim re-
sistor so that the output voltage is equal to the desired full scale
minus 1 LSB plus the offset error measured in step 1.
Step 3 – Reset all bits to Logic “0” (OFF). Adjust the offset
trim resistor for 0 V output.
DIGITAL
INPUTSFigure 6.Unbuffered Unipolar Gain and Zero Adjust
BIPOLAR MODE (Refer to Figure 7)
Step 1 – Set bits to offset binary “zero” (10 . . . 00). Adjust the
zero resistor to produce 0 V at the DAC output. This removes
the bipolar zero error.
Step 2 – Set all bits to Logic “1” (ON). Adjust gain trim resistor
so the output voltage is equal to the desired full-scale minus
full scale at the DAC output. Note: this may slightly compro-
mise the bipolar zero trim.
Figure 7.Bipolar Unbuffered Gain and Zero Adjust
BUFFERED VOLTAGE OUTPUTFor full-scale outputs of greater than 1 V, some type of external
buffer amplifier is required. The AD840 fills this requirement
perfectly, settling to 0.025% from a 10 V full-scale step in less
than 100 ns.
A 1 kΩ span resistor has been provided on chip for use as a
feedback resistor in buffered applications. Using RSPAN (Pins 15,
16) introduces a 100 mW code-dependent power source onto
the chip which may generate a slight degradation in linearity.
Maximum linearity performance can be realized by using an ex-
ternal span resistor.
Figure 8.Unipolar Output Buffered 0 to –10.24V
Unipolar Inverting ConfigurationFigure 8 shows the connections for producing a – 10.24 V full-
scale swing. This configuration uses the AD568 in the current
output mode into a summing junction at the inverting input ter-
minal of the external op amp. With the load resistor RL
AD568sation capacitor across the 1 kΩ feedback resistor produces opti-
mal settling. Lower noise gain can be achieved by connecting RL
to IOUT, increasing the DAC output impedance to approximately
200 Ω, and reducing the noise gain to 6 (illustrated in Figure 9).
While the output in this configuration will feature improved
noise performance, it is somewhat less stable and may suffer
from ringing. The compensation capacitance should be in-
creased to 7 pF to maintain stability at this reduced gain.
DIGITAL
INPUTS
–15V+15VDIGITAL
SUPPLY
GROUND
+5V
AMPLIFIER NOISE GAIN: 11Figure 8.Unipolar Output Buffered 0 to –10.24V
DIGITAL
INPUTS
–15V+15VDIGITAL
SUPPLY
GROUND
+5VFigure 9.Bipolar Output Buffered ±5.12 V
Bipolar Inverting ConfigurationFigure 9 illustrates the implementation of a +5.12 V to –5.12 V
Noninverting ConfigurationIf a positive full-scale output voltage is required, it can be imple-
mented using the AD568 in the unbuffered voltage output mode
followed by the AD840 in a noninverting configuration (Figure
10). The noise gain of this topology is 10, requiring only 5 pF
across the feedback resistor to optimize settling.
DIGITAL
INPUTS
–15V+15V
DIGITAL
SUPPLY
GROUND
+5VFigure 10.Unipolar Output Buffered 0 V to +10.24 V
Guidelines for Using the AD568The designer who seeks to combine high speed with high preci-
sion faces a challenging design environment. Where tens of
milliamperes are involved, fractions of an ohm of misplaced
impedance can generate several LSBs of error. Increasing
bandwidths make formerly negligible parasitic capacitances and
inductances significant. As system performance reaches and ex-
ceeds that of the measurement equipment, time-honored test
methods may no longer be trustworthy. The DAC’s placement
on the boundary between the analog and digital domains intro-
duces additional concerns. Proper RF techniques must be used
in board design, device selection, supply bypassing, grounding,
and measurement if optimal performance is to be realized. The
AD568 has been configured to be relatively easy to use, even in
some of the more treacherous applications. The device charac-
teristics shown in this data sheet are readily achievable if proper
attention is paid to the details. Since a solid understanding of
the circuit involved is one of the designer’s best weapons against
the difficulties of RF design, the following sections provide illus-
trations, explanations, examples, and suggestions to facilitate
successful design with the AD568.
Current Output vs. Voltage OutputAs indicated in Figures 3 through 10, the AD568 has been
designed to operate in several different modes depending on the
external circuit configuration. While these modes may be
categorized by many different schemes, one of the most impor-
tant distinctions to be made is whether the DAC is to be used to
The threshold of the digital inputs is set at 1.4 V and does not
vary with supply voltage. This is provided by a bandgap refer-
ence generator, which requires approximately 3 mA of bias cur-
rent achieved by tying RTH to any +VL supply where
RTH=+VL±1.4V
3mA
The input lines operate with small input currents to easily
achieve interface with unbuffered CMOS logic. The digital in-
put signals to the DAC should be isolated from the analog out-
put as much as possible. To minimize undershoot, ringing, and
possible digital feedthrough noise, the interconnect distances to
the DAC inputs should be kept as short as possible. Termina-
tion resistors may improve performance if the digital lines be-
come too long. The digital input should be free from large
glitches and ringing and have maximum 10% to 90% rise and
fall times of 5 ns. Figure 12 shows the equivalent digital input
circuit of the AD568.
Figure 12.Equivalent Digital Input
Due to the high-speed nature of the AD568, it is recommended
that high-speed logic families such as Schottky TTL, high-speed
CMOS, or the new lines of FAST* TTL be used exclusively.
Table I shows how DAC performance can vary depending on
the driving logic used. As this table indicates, STTL, HCMOS,
and FAST represent the most viable families for driving the
AD568.
Table I.DAC Performance vs. Drive Logic1NOTESAll values typical, taken in rest fixture diagrammed in Figure 13.Measurements are made for a 1 V full-scale step into 100 Ω DAC load
resistance.Settling time is measured from the time the digit input crosses the threshold
voltage (1.4 V) to when the output is within the specified range of its final
value.The worst case glitch impulse, measured on the major carry DAC full scale
is 1 V.
mode, the DAC output scale is insensitive to whether the load
resistor, RL, is shorted (Pin 19 connected to Pin 20), or
grounded (Pin 19 connected to Pin 18). However, this does
affect the output impedance of the DAC current and may have a
significant impact on the noise gain of the external circuitry. In
the voltage output mode, the DAC’s output current flows
through its own internal impedance (perhaps in parallel with an
external impedance) to generate a voltage, as in Figures 3, 4, 5,
and 10. In this case, the DAC output scale is directly dependent
on the load impedance. The temperature coefficient of the
AD568’s internal reference is trimmed in such a way that the
drift of the DAC output in the voltage output mode is centered
on zero. The current output of the DAC will have an additional
drift factor corresponding to the absolute temperature coeffi-
cient of the internal thin-film resistors. This additional drift may
be removed by judicious placement of the 1 kΩ span resistor in
the signal path. For example, in Figures 8 and 9, the current
flowing from the DAC into the summing junction could suffer
from as much as 150 ppm/°C of thermal drift. However, since
this current flows through the internal span resistor (Pins 15 and
16) which has a temperature coefficient that matches the DAC
ladder resistors, this drift factor is compensated and the buffered
voltage at the amplifier output will be within specified limits for
the voltage output mode.
Output Voltage ComplianceThe AD568 has a typical output compliance range of +1.2 V to
–2.0 V (with respect to the LCOM Pin). The current-
steering output stages will be unaffected by changes in the out-
put terminal voltage over that range. However, as shown in Fig-
ure 11, there is an equivalent output impedance of 200 Ω in
parallel with 15 pF at the output terminal which produces an
equivalent error current if the voltage deviates from the ladder
common. This is a linear effect which does not change with in-
put code. Operation beyond the maximum compliance limits
may cause either output stage saturation or breakdown resulting
in nonlinear performance. The positive compliance limit is not
affected by the positive power supply, but is a function of output
current and the logic threshold voltage at VTH, Pin 13.
IOUT = 10.24mA xDIGITAL IN
4096IOUT = 10.24mA xDIGITAL IN
ANALOG
COMMON
LADDER
COMMON
RLOAD
(200Ω)
COMPLIANCE
TO VTHRESHOLD
RLOADIOUT
COMPLIANCE TO
LOGIC LOW VALUE
(1 – )Figure 11.Equivalent Output
Digital Input ConsiderationsThe AD568 uses a standard positive true straight binary code
for unipolar outputs (all 1s full-scale output), and an offset bi-
nary code for bipolar output ranges. In the bipolar mode, with
all 0s on the inputs, the output will go to negative full scale;
with 111 . . . 11, the output will go to positive full scale less
