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AD561JD-AD561JN-AD561KD-AD561KN-AD561SD
Low Cost 10-Bit Monolithic D/A Converter
REV.A
Low Cost 10-Bit
Monolithic D/A Converter
FUNCTIONAL BLOCK DIAGRAM
TO-116
PRODUCT DESCRIPTIONThe AD561 is an integrated circuit 10-bit digital-to-analog
converter combined with a high stability voltage reference
fabricated on a single monolithic chip. Using ten precision high-
speed current-steering switches, a control amplifier, voltage
reference, and laser-trimmed thin-film SiCr resistor network,
the device produces a fast, accurate analog output current.
Laser trimmed output application resistors are also included to
facilitate accurate, stable current-to-voltage conversion; they are
trimmed to 0.1% accuracy, thus eliminating external trimmers
in many situations.
Several important technologies combine to make the AD561 the
most accurate and most stable 10-bit DAC available. The low
temperature coefficient, high stability thin-film network is
trimmed at the wafer level by a fine resolution laser system to
0.01% typical linearity. This results in an accuracy specification
of ±1/4 LSB max for the K and T versions, and 1/2 LSB max
for the J and S versions.
The AD561 also incorporates a low noise, high stability
subsurface zener diode to produce a reference voltage with
excellent long term stability and temperature cycle characteris-
tics, which challenge the best discrete Zener references. A
temperature compensation circuit is laser-trimmed to allow
custom correction of the temperature coefficient of each device.
This results in a typical full-scale temperature coefficient of
15 ppm/°C; the TC is tested and guaranteed to 30 ppm/°C max
for the K and T versions, 60 ppm/°C max for the S, and
80 ppm/°C for the J.
The AD561 is available in four performance grades. The
AD561J and K are specified for use over the 0°C to +70°C
temperature range and are available in either a 16-pin
FEATURES
Complete Current Output Converter
High Stability Buried Zener Reference
Laser Trimmed to High Accuracy (1/4 LSB Max Error,
AD561K, T)
Trimmed Output Application Resistors for 0 V to +10 V,65 V Ranges
Fast Settling – 250 ns to 1/2 LSB
Guaranteed Monotonicity Over Full Operating
Temperature Range
TTL/DTL and CMOS Compatible (Positive True Logic)
Single Chip Monolithic Construction
Available in Chip Form
MlL-STD-883-Compliant Versions Availablehermetically-sealed ceramic DIP or a 16-pin molded plastic
DIP. The AD561S and T grades are specified for the –55°C to
+125°C range and are available in the ceramic package.
PRODUCT HIGHLIGHTSAdvanced monolithic processing and laser trimming at the
wafer level have made the AD561 the most accurate 10-bit
converter available, while keeping costs consistent with large
volume integrated circuit production. The AD561K and T
have 1/4 LSB max relative accuracy and 1/2 LSB max
differential nonlinearity. The low TC R-2R ladder guaran-
tees that all AD561 units will be monotonic over the entire
operating temperature range.Digital system interfacing is simplified by the use of a
positive true straight binary code. The digital input voltage
threshold is a function of the positive supply level; connect-
ing VCC to the digital logic supply automatically sets the
threshold to the proper level for the logic family being used.
Logic sink current requirement is only 25 μA.The high speed current steering switches are designed to settle
in less than 250 ns for the worst case digital code transition.
This allows construction of successive-approximation A/D
converters in the 3 μs to 5 μs range.The AD561 has an output voltage compliance range from
–2 V to +10 V, allowing direct current-to-voltage conversion
with just an output resistor, omitting the op amp. The 40 MΩ
open collector output impedance results in negligible errors
due to output leakage currents.The AD561 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD561/883B data sheet for detailed
specifications.
AD561–SPECIFICATIONSDATA INPUTS
OUTPUT
SETTLING TIME TO 1/2 LSB
POWER REQUIREMENTS
MONOTONICITY
PROGRAMMABLE OUTPUT
CALIBRATION ACCURACY
CALIBRATION ADJUSTMENT
(TA = +258C, VCC = –15 V, unless otherwise noted.)
AD561DATA INPUTS
OUTPUT
SETTLING TIME TO 1/2 LSB
POWER REQUIREMENTS
TEMPERATURE COEFFICIENTS
MONOTONICITY
PROGRAMMABLE OUTPUT
CALIBRATION ACCURACY
CALIBRATION ADJUSTMENT
AD561
THE AD561 OFFERS TRUE 10-BIT RESOLUTION OVER
FULL TEMPERATURE RANGE
Accuracy: Analog Devices defines accuracy as the maximumdeviation of the actual, adjusted DAC output (see page 5) from
the ideal analog output (a straight line drawn from 0 to FS – l
LSB) for any bit combination. The AD561 is laser trimmed to
1/4 LSB (0.025% of FS) maximum error at +25°C for the K
and T versions – 1/2 LSB for the J and S.
Monotonicity: A DAC is said to be monotonic if the outputeither increases or remains constant for increasing digital inputs
such that the output will always be a single-valued function of the
input. All versions of the AD561 are monotonic over their full
operating temperature range.
Differential Nonlinearity: Monotonic behavior requires thatthe differential nonlinearity error be less than
1 LSB both at +25°C and over the temperature range of
interest. Differential nonlinearity is the measure of the variation
in analog value, normalized to full scale, associated with a
1 LSB change in digital input code. For example, for a 10 volt
full scale output, a change of 1 LSB in digital input code should
result in a 9.8 mV change in the analog output (1 LSB = 10 V
× 1/1024 = 9.8 mV). If in actual use, however, a 1 LSB change
in the input code results in a change of only 2.45 mV (1/4 LSB)
in analog output, the differential nonlinearity error would be
7.35 mV, or 3/4 LSB The AD561K and T have a max differen-
tial linearity error of 1/2 LSB.
The differential nonlinearity temperature coefficient must also
be considered if the device is to remain monotonic over its full
operating temperature range. A differential nonlinearity tempera-
ture coefficient of 2.5 ppm/°C could, under worst case condi-
tions for a temperature change of +25°C to +125°C, add 0.025%
(100 3 2.5 ppm/°C of error). The resulting error could then be
as much as 0.025% + 0.025% = 0.05% of FS (1/2 LSB represents
0.05% of FS). To be sure of accurate performance all versions of
the AD561 are therefore 100% tested to be monotonic over the
full operating temperature range.
Figure 1.Chip Bonding Diagram
CONNECTING THE AD561 FOR BUFFERED VOLTAGE
OUTPUTThe standard current-to-voltage conversion connections using
an operational amplifier are shown here with the preferred
trimming techniques. If a low offset operational amplifier
(AD510, AD741L, AD301AL) is used, excellent performance
can be obtained in many situations without trimming. (A 5 mV
op amp offset is equivalent to 1/2 LSB on a 10 volt scale.) If a
25 Ω fixed resistor is substituted for the 50 Ω trimmer, unipolar
zero will typically be within ±1/10 LSB (plus op amp offset),
and full scale accuracy will be within ±1 LSB. Substituting a
25 Ω resistor for the 50 Ω bipolar offset trimmer will give a
bipolar zero error typically within ±1 LSB.
The AD509 is recommended for buffered voltage-output
applications that require a settling time to ±1/2 LSB of one
microsecond. The feedback capacitor is shown with the
optimum value for each application; this capacitor is required to
compensate for the 25 picofarad DAC output capacitance.
ORDERING GUIDENOTESFor details on grade and package offerings screened in accordance with MIL-STD-883, refer to the
Analog Devices Military Products Databook or current AD561/883B data sheet.D = Ceramic DIP; N = Plastic DIP.
*Refer to AD561/883B military data sheet.
PIN CONFIGURATION
TOP VIEW
UNIPOLAR CONFIGURATIONThis configuration, shown in Figure 2, will provide a unipolar
0 V to +10 V output range.
STEP I . . . ZERO ADJUSTTurn all bits OFF and adjust op amp trimmer, R1, until the
output reads 0.000 volts (1 LSB = 9.76 mV).
STEP 11. . . GAIN ADJUSTTurn all bits ON and adjust 50 Ω gain trimmer, R2, until the
output is 9.990 volts. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 volts.) If a 10.23 V full scale is desired
(exactly 10 mV/bit), insert a 120 Ω resistor in series with R2.
BIPOLAR CONFIGURATIONThis configuration, shown in Figure 3, will provide a bipolar
output voltage from –5.000 to +4.990 volts, with positive full
scale occurring with all bits ON (all 1s).
STEP 1. . . ZERO ADJUSTTurn ON MSB only, turn OFF all other bits. Adjust 50 Ω
trimmer R3, to give 0.000 output volts. For maximum resolution
a 120 Ω resistor may be placed in parallel with R3.
STEP 11. . . GAIN ADJUSTTurn OFF all bits, adjust 50 Ω gain trimmer to give a reading of
–5.000 volts.
Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
the op amp trimmer is unnecessary unless the untrimmed offset
drift of the op amp is excessive.
610 VOLT BUFFERED BIPOLAR OUTPUT
The AD561 can also be connected for a ±10 volt bipolar range
with an additional external resistor as shown in Figure 4. A
larger value trimmer is required to compensate for tolerance in
the thin film resistors, which are trimmed to match the full-scale
current. For best full scale temperature coefficient performance,
the external resistors should have a TC of –50 ppm/°C.
CIRCUIT DESCRIPTIONA simplified schematic with the essential circuit features of the
AD561 is shown in Figure 5. The voltage reference, CR1, is a
buried Zener (or subsurface breakdown diode). This device
exhibits far better all-around performance than the NPN base-
emitter reverse-breakdown diode (surface Zener), which is in
nearly universal use in integrated circuits as a voltage reference.
Greatly improved long-term stability and lower noise are the
major benefits the buried Zener derives from isolating the
breakdown point from surface stress and mobile oxide charge
effects. The nominal 7.5 volt device (including temperature
compensation circuitry) is driven by a current source to the
negative supply so the positive supply can be allowed to drop as
low as 4.5 volts. The temperature coefficient of each diode is
individually determined; this data is then used to laser trim a
compensating circuit to balance the overall TC to zero. The
typical resulting TC is 0 to ±15 ppm/°C. The negative reference
level is inverted and scaled by A1 to give a +2.5 volt reference,
which can be driven by the low positive supply. The AD561,
packaged in the 16-pin DIP, has the +2.5 volt reference (REF
OUT) connected directly to the input of the control amplifier
The 2.5 kΩ scaling resistor and control amplifier A2 then force a
1 mA reference current to flow through reference transistor Q1,
which has a relative emitter area of 8A. This is accomplished by
forcing the bottom of the ladder to the proper voltage. Since Q1
and Q2 have equal emitter areas and equal 5 kΩ emitter resistors,
Q2 also carries 1 mA. The ladder voltage drop constrains Q7
(with area 4A) to carry only 0.5 mA; Q8 carries 0.25 mA, etc.
The first four significant bit cells are exactly scaled in emitter
area to match Q1 for optimum VBE and VBE drift match, as well
as for beta match. These effects are insignificant for the lower
order bits, which account for a total of only 1/16 of full scale.
However, the 18 mV VBE difference between two matched
transistors carrying emitter currents in a ratio of 2:1 must be
corrected. This is achieved by forcing 120 μA through the
150 Ω interbase resistors. These resistors, and the R-2R ladder
resistors, are actively laser-trimmed at the wafer level to bring
Figure 2.0 V to +10 V Unipolar Voltage Output
Figure 3.±5 V Buffered Bipolar Voltage Output
Figure 4.±10 V Buffered Voltage Output
AD561ratio such that it is unnecessary to use additional area for ladder
resistors. The current in Q16 is added to the ladder to balance it
properly, but is not switched to the output; thus, full scale is
1023/1024 3 2 mA.
The switching cell of Q3, Q4, Q5 and Q6 serves to steer the cell
current either to ground (BIT 1 low) or to the DAC output
(BIT 1 high). The entire switching cell carries the same current
whether the bit is on or off, minimizing thermal transients and
ground current errors. The logic threshold, which is generated
from the positive supply (see Digital Logic Interface), is applied
to one side of each cell.
Figure 6.Digital Threshold vs. Positive Supply
DIGITAL LOGIC INTERFACEAll standard positive supply logic families interface easily with
the AD561. The digital code is positive true binary (all bits
high, Logic “1,” gives positive full scale output). The logic input
load factor (100 nA max at Logic “1,” –25 μA max at Logic “0,”
3 pF capacitance), is less than one equivalent digital load for all
logic families, including unbuffered CMOS. The digital
threshold is set internally as a function of the positive supply, as
will assume a “1” state (similar to TTL), but they are high
impedance and subject to noise pickup. Unused digital inputs
should be directly connected to ground or VCC, as desired.
SETTLING TIMEThe high speed NPN current steering switching cell and
internally compensated reference amplifier of the AD561 are
specifically designed for fast settling operation. The typical
settling time to ±0.05% (1/2 LSB) for the worst case transition
(major carry, 0111111111 to 1000000000) is less than 250 ns;
the lower order bits all settle in less than 200 ns. (Worst case
settling occurs when all bits are switched, especially the MSB.)
Full realization of this high speed performance requires strict
attention to detail by the user in all areas of application and
testing.
The settling time for the AD561 is specified in terms of the
current output, an inherently high speed DAC operating mode.
However, most DAC applications require a current-to-voltage
conversion at some point in the signal path, although an
unbuffered voltage level (not using an op amp) is suitable for
use in a successive-approximation A/D converter (see page 8),
or in many display applications. This form of conversion can
give very fast operation if proper design and layout is done. The
fastest voltage conversion is achieved by connecting a low value
resistor directly to the output, as shown in Figure 9. In this case,
the settling time is primarily determined by the cell switching
time and by the RC time constant of the AD561 output capaci-
tance of 25 picofarads (plus stray capacitance) combined with the
output resistor value. Settling to 0.05% of full scale (for a full-
scale transition) requires 7.6 time constants. This effect is
important for R > 1 kΩ.
If an op amp must be used to provide a low impedance output
signal, some loss in settling time will be seen due to op amp
dynamics. The normal current-to-voltage converter op amp
circuits are shown in the applications circuits on page 5, using
the fast settling AD509. The circuits shown settle to ±1/2 LSB
in 600 ns unipolar and 1.1 μs bipolar. The DAC output
capacitance, which acts as a stray capacitance at the op amp
inverting input, must be compensated by a feedback capacitor,
Figure 5.Circuit Diagram Showing Reference, Control Amplifier, Switching Cell, R-2R Ladder, and Bit Arrangement
of AD561
