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AD5601BKS-AD5621AKS
2.7 V to 5.5 V,
2.7 V to 5.5 V, <100 µA, 8-/10-/12-Bit
nanoDAC™ D/A, SPI® Interface, SC70 Package
Rev. PrC
FEATURES
6-lead SC70 package
Power-down to <100 nA @ 3 V
Micropower operation: max 100 µA @ 5 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
SYNC interrupt facility
Minimized zero code error
AD5601 buffered 8-bit DAC in SC70:
B Version: ±0.5 LSB INL
AD5611 buffered 10-bit DAC in SC70:
B Version: ±0.5 LSB INL
A Version: ±4 LSB INL
AD5621 buffered 12-bit DAC in SC70:
B Version: ±1 LSB INL
A Version: ±6 LSB INL
APPLICATIONS
Voltage level setting
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAM
SYNCSCLKDINFigure 1.
Table 1. Related Devices
GENERAL DESCRIPTION The AD5601/AD5611/AD5621, members of the nanoDAC
family, are single, 8-/10-/12-bit, buffered, voltage out DACs that
operate from a single 2.7 V to 5.5 V supply, consuming <100 µA
at 5 V. The parts come in a tiny SC70 package. Their on-chip
precision output amplifier allows rail-to-rail output swing to be
achieved. The AD5601/AD5611/AD5621 utilize a versatile
3-wire serial interface that operates at clock rates up to 30 MHz
and is compatible with SPI®, QSPI™, MICROWIRE™, and DSP
interface standards.
The reference for the AD5601/AD5611/AD5621 is derived from
the power supply inputs and, therefore, gives the widest
dynamic output range. The parts incorporate a power-on reset
circuit, which ensures that the DAC output powers up to 0 V
and remains there until a valid write to the device takes place.
The AD5601/AD5611/AD5621 contain a power-down feature
that reduces current consumption to <100 nA at 3 V, and
provides software-selectable output loads while in power-down
mode. The parts are put into power-down mode over the serial
interface. The low power consumption of these parts in normal
operation makes them ideally suited to portable battery-
operated equipment. The combination of small package and low
power makes these nanoDAC devices ideal for level-setting
requirements such as generating bias or control voltages in
space-constrained and power-sensitive applications.
(continued on Page 3)
TABLE OF CONTENTS Product Highlights...........................................................................3
Specifications.....................................................................................4
Timing Characteristics................................................................5
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Pin Configuration and Function DescriptionS............................7
Terminology......................................................................................8
Typical Performance Characteristics.............................................9
General Description.......................................................................13
D/A Section.................................................................................13
Resistor String.............................................................................13
Output Amplifier........................................................................13
Serial Interface............................................................................13
Input Shift Register....................................................................13
SYNC Interrupt..........................................................................14
Power-On Reset..........................................................................14
Power-Down Modes..................................................................14
Microprocessor Interfacing.......................................................14
Applications.....................................................................................16
Choosing a Reference as Power Supply for
AD5601/AD5611/AD5621.......................................................16
Bipolar Operation Using the AD5601/ AD5611/AD5621....16
Using AD5601/AD5611/AD5621 with an Opto-Isolated
Interface.......................................................................................17
Power Supply Bypassing and Grounding................................17
Outline Dimensions.......................................................................18
Ordering Guide..........................................................................18
REVISION HISTORY Revision PrC: Preliminary Version
PRODUCT HIGHLIGHTS 1. Available in a space-saving 6-lead SC70 package.
2. Low power, single-supply operation. The AD5601/
AD5611/AD5621 operate from a single 2.7 V to 5.5 V
supply and typically consume 0.2 mW at 3 V and 0.5 mW
at 5 V, making them ideal for battery-powered applications.
3. The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/µs.
4. Reference derived from the power supply.
5. High speed serial interface with clock speeds up to
30 MHz.
6. Designed for very low power consumption. The interface
powers up only during a write cycle.
7. Power-down capability. When powered down, the DAC
typically consumes <100 nA at 3 V.
SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. Temperature ranges are as follows: B Version: –40°C to +125°C, typical at +25°C.
2 Linearity calculated using a reduced code range. Guaranteed by design and characterization, not production tested.
TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.
Table 3. All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 30 MHz.
DIN
SYNC
SCLK04783-C-002
Figure 2. Timing Diagram
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 4. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD
GNDSCLK
DIN
VOUTSYNC04783-C-003
Figure 3. 6-Lead SC70 Pin Configuration
Table 5. Pin Function Descriptions TERMINOLOGY
Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL versus code plot can be seen in Figure 4.
Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL versus code plot can be
seen in Figure 7.
Zero-Code Error Zero-code error is a measure of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5601/AD5611/AD5621, because the output of the DAC
cannot go below 0 V. Zero-code error is due to a combination of
the offset errors in the DAC and output amplifier. Zero-code
error is expressed in mV. A plot of zero-code error versus
temperature can be seen in Figure 6.
Full-Scale Error Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
should be VDD − 1 LSB. Full-scale error is expressed in percent
of full-scale range. A plot of full-scale error versus temperature
can be seen in Figure 6.
Gain Error Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal,
expressed as a percent of the full-scale range.
Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error
taking all the various errors into account. A typical TUE versus
code plot can be seen in Figure 5.
Zero-Code Error Drift Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in µV/°C.
Gain Error Drift Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 17.
Digital Feedthrough Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It is
specified in nV-s and is measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
TYPICAL PERFORMANCE CHARACTERISTICS
CODE04783-C-004
2.52k4k6k8k10k12k14k16k
RRO
R (Figure 4. Typical INL Plot
2562k4k6k8k10k12k14k16k
TUE (LS
CODE04783-C-005
Figure 5. Total Unadjusted Error
Figure 6. Zero-Scale Error and Full-Scale Error vs. Temperature
0.52k4k6k8k10k12k14k16k
DNL E
RROR (LS
CODE04783-C-007
Figure 7. Typical DNL Plot
Figure 8. INL and DNL vs. Supply
Figure 9. IDD Histogram @ VDD = 3 V/5 V
I(mA)04783-C-010
Figure 10. Source and Sink Current Capability
Figure 11. Supply Current vs. Temperature
Figure 12. Full-Scale Settling Time
Figure 13. Supply Current vs. Code
Figure 14. Supply Current vs. Supply Voltage
Figure 15. Half-Scale Settling Time
