AD5545BRU ,Precision DUAL 16-Bit and 14-Bit DACs in Compact TSSOP PackagesCHARACTERISTICS Table 1. VDD = 5 V ± 10%, IOUT = Virtual GND, GND = 0 V, VREF = 10 V, TA = Full Ope ..
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AD557JNZ , DACPORT Low Cost, Complete μP-Compatible 8-Bit DAC
AD557JP-REEL ,DACPORT Low Cost, Complete µP-Compatible 8-Bit DAC
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AD96685BH ,Ultrafast ComparatorsaUltrafast ComparatorsAD96685/AD96687
AD96685BP ,Ultrafast ComparatorsCHARACTERISTICS4Input Offset Voltage +25°CI 1 2 12 12 12 mVFull VI 3333mVInput Offset Drift Full V ..
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AD5545BRU
Precision DUAL 16-Bit and 14-Bit DACs in Compact TSSOP Packages
Dual, Current-Output,
Serial-Input, 16-/14-Bit DAC
Rev. 0
FEATURES
16-bit resolution AD5545
14-bit resolution AD5555
±1 LSB DNL monotonic
±2 LSB INL AD5545
2 mA full-scale current ±20%, with VREF = 10 V
0.5 µs settling time
2Q multiplying reference-input 4 MHz BW
Zero or midscale power-up preset
Zero or midscale dynamic reset
3-wire interface
Compact TSSOP-16 package
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
Industrial control PLCs
Programmable attentuator
PRODUCT OVERVIEW The AD5545/AD5555 are 16-bit/14-bit, current-output, digital-
to-analog converters designed to operate from a single 5 V
supply with bipolar output up to ±15 V capability.
An external reference is needed to establish the full-scale out-
put-current. An internal feedback resistor (RFB) enhances the
resistance and temperature tracking when combined with an
external op amp to complete the I-to-V conversion.
A serial data interface offers high speed, 3-wire microcontroller
compatible inputs using serial data in (SDI), clock (CLK), and
chip select (CS). Additional LDAC function allows simultane-
ous update operation. The internal reset logic allows power-on
preset and dynamic reset at either zero or midscale, depending
on the state of the MSB pin.
The AD5545/AD5555 are packaged in the compact TSSOP-16
package and can be operated from –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
VDDRFBA
VREFBVREFA
IOUTA
AGNDA
SDI
CLK
DGNDMSBRSLDAC
RFBB
IOUTB
AGNDB
02918-0-001 Figure 1.
TABLE OF CONTENTS AD5545/AD5555—Electrical Characteristics..............................3
Absolute Maximum Ratings............................................................5
Pin Configuration And Functional Descriptions.........................6
Typical Performance Characteristics.............................................9
Circuit Operation...........................................................................11
D/A Converter Section..............................................................11
Serial Data Interface...................................................................11
Power-Up Sequence...................................................................12
Layout and Power Supply Bypassing.......................................12
Grounding...................................................................................12
Applications.....................................................................................13
Stability........................................................................................13
Positive Voltage Output.............................................................13
Bipolar Output............................................................................13
Programmable Current Source................................................13
DAC with Programmable Input Reference Range................14
Outline Dimensions.......................................................................16
ESD Caution................................................................................16
Ordering Guide..........................................................................16
REVISION HISTORY Revision 0: Initial Version
AD5545/AD5555—ELECTRICAL CHARACTERISTICS
Table 1. VDD = 5 V ± 10%, IOUT = Virtual GND, GND = 0 V, VREF = 10 V, TA = Full Operating Tempearture Range,
unless otherwise noted. All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 RFB terminal
is tied to the amplifier output. Typical values represent average readings measured at 25°C.
ABSOLUTE MAXIMUM RATINGS
Table 2. AD5545/AD5555 Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
DGND
CLK
VDD
MSB
LDAC
SDI
VREFB
RFBB
IOUTB
RFBA
IOUTA
VREFA
02918-0-002 Figure 2. 16-Lead TSSOP
Table 3. Pin Function Descriptions—16-Lead TSSOP 02918-0-003SDI
CLK
tLDACtLDHLDACFigure 3. AD5545 18-Bit Data Word Timing Diagram
02918-0-004SDI
CLK
tLDACtLDHLDACFigure 4. AD5555 16-Bit Data Word Timing Diagram
Table 4. AD5545 Control Logic Truth Table NOTES
1. SR = Shift Register, ↑+ = Positive Logic Transition, and X = Don’t Care.
Table 5. AD5555 Control Logic Truth Table NOTES
1. SR = Shift Register, ↑+ = Positive Logic Transition, and X = Don’t Care.
2. At power-on, both the input register and the DAC register are loaded with all 0s.
Table 6. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format Note that only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D15–D0) to the
decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5545 shift register are ignored; only
the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 7. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format Note that only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D13–D0) to the
decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5555 shift register are ignored; only
the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 8. Address Decode
