AD5544 Fast Delivery |IC PHOENIX CO.,LIMITED

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AD96685BH ,Ultrafast ComparatorsaUltrafast ComparatorsAD96685/AD96687
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AD5544
Precision QUAD 16-Bit DAC
REV.0
Quad, Current-Output
Serial-Input, 16-Bit/14-Bit DACs
FUNCTIONAL BLOCK DIAGRAM
VDD
RFBA
IOUTA
AGNDA
AGNDF
VSSLDACMSBRSDGND
CLK
SDI
SDO
VREF ABCD
RFBB
IOUTB
AGNDB
RFBC
IOUTC
AGNDC
RFBD
IOUTD
AGNDD
FEATURES
AD5544 16-Bit Resolution
AD5554 14-Bit Resolution
2 mA Full-Scale Current �20%, with VREF = �10 V
2 �s Settling Time
VSS BIAS for Zero-Scale Error Reduction @ Temp
Midscale or Zero-Scale Reset
Four Separate 4Q Multiplying Reference Inputs
SPI-Compatible 3-Wire Interface
Double Buffered Registers Enable
Simultaneous Multichannel Change
Internal Power ON Reset
Compact SSOP-28 Package
APPLICATIONS
Automatic Test Equipment
Instrumentation
Digitally-Controlled Calibration
GENERAL DESCRIPTION
The AD5544/AD5554 quad, 16-/14-bit, current-output, digital-
to-analog converters are designed to operate from a single 5V
supply.
The applied external reference input voltage (VREF) determines
the full-scale output current. Integrated feedback resistors (RFB)
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision ampliﬁer.
A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI- and microcontroller-compatible inputs using
serial-data-in (SDI), clock (CLK), and a chip-select (CS). In
addition, a serial-data-out pin (SDO) allows for daisy-chaining
when multiple packages are used. A common level-sensitive
load-DAC strobe (LDAC) input allows simultaneous update of
all DAC outputs from previously loaded input registers. Addi-
tionally, an internal power ON reset forces the output voltage to
zero at system turn ON. An MSB pin allows system reset asser-
tion (RS) to force all registers to zero code when MSB = 0, or
to half-scale code when MSB = 1.
AD5544/AD5554 are packaged in the compact SSOP-28.
Figure 1.AD5544 INL vs. Code Plot (TA = 25°C)
AD5544/AD5554–SPECIFICATIONS
AD5544 ELECTRICAL CHARACTERISTICS
SUPPLY CHARACTERISTICS
NOTESAll static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter ampliﬁer. The AD5544
RFB terminal is tied to the ampliﬁer output. Typical values represent average readings measured at 25°C.These parameters are guaranteed by design and not subject to production testing.All input control signals are speciﬁed with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Speciﬁcations subject to change without notice.
(@ VDD = 5 V � 10%, VSS = 0 V, IOUTX = Virtual GND, AGNDX = 0 V,
VREFA, B, C, D = 10 V, TA = Full Operating Temperature Range,
unless otherwise noted.)
AD5544 ELECTRICAL CHARACTERISTICS
NOTESAll ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter ampliﬁer.
Speciﬁcations subject to change without notice.
(@ VDD = 5 V � 10%, VSS = –300 mV, IOUTX = Virtual GND, AGNDX = 0 V,
VREFA, B, C, D = 10 V, TA = full operating temperature range, unless
otherwise noted.)
AD5544/AD5554–SPECIFICATIONS
AD5554 ELECTRICAL CHARACTERISTICS
NOTES:All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter ampliﬁer. The AD5554
RFB terminal is tied to the ampliﬁer output. Typical values represent average readings measured at 25°C.These parameters are guaranteed by design and not subject to production testing.All input control signals are speciﬁed with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Speciﬁcations subject to change without notice.
(@ VDD = 5 V � 10%, VSS = 0 V, IOUTX = Virtual GND, AGNDX = 0 V,
VREFA, B, C, D = 10 V, TA = full operating temperature range,
unless otherwise noted.)
AD5554 ELECTRICAL CHARACTERISTICS
NOTES:All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter ampliﬁer.
Speciﬁcations subject to change without notice.
(@ VDD = 5 V � 10%, VSS = –300 mV, IOUTX = Virtual GND, AGNDX = 0 V, VREFA,
B, C, D = 10 V, TA = full operating temperature range, unless otherwise
noted.)
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–18 V, +18 V
Logic Inputs and Output to GND . . . . . . . . . . . .–0.3 V, +8 V
V(IOUT) to GND . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
AGNDX to DGND . . . . . . . . . . . . . . . . . . . . . .–0.3 V, + 0.3 V
Input Current to Any Pin Except Supplies . . . . . . . . . ±50 mA
Package Power Dissipation . . . . . . . . . . . .(TJ MAX – TA)/θJA
Thermal Resistance θJA
28-Lead Shrink Surface-Mount (RS-28) . . . . . . . .100°C/W
Maximum Junction Temperature (TJ MAX) . . . . . . . . . 150°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5544/AD5554 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
The AD5544/AD5554 contain 4196 transistors. The die size is 122 mil × 204 mil.
Operating Temperature Range
Model A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature:
RS-28 (Vapor Phase, 60 secs) . . . . . . . . . . . . . . . . . . 215°C
RS-28 (Infrared, 15 secs) . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD5544/AD5554
Figure 2.AD5544 Timing Diagram
Figure 3.AD5554 Timing Diagram
Table I.AD5544 Control-Logic Truth Table
Table II.AD5554 Control-Logic Truth Table
NOTESSR = Shift Register.↑+ positive logic transition; X = Don’t Care.At power ON both the Input Register and the DAC Register are loaded with all zeros.For AD5544, data appears at the SDO Pin 19 clock pulses after input at the SDI pin.For AD5554, data appears at the SDO Pin 17 clock pulses after input at the SDI pin.
Table III.AD5544 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSBLSB
NOTE
Only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge returns to logic high. At this point an inter-
nally generated load strobe transfers the serial register data contents (Bits D15–D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any
extra bits clocked into the AD5544 shift register are ignored, only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied
logic low to disable the DAC Registers.
Table IV.AD5554 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSBLSB
Bit Position
NOTE
Only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge returns to logic high. At this point an inter-
nally generated load strobe transfers the serial register data contents (Bits D13–D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any
extra bits clocked into the AD5554 shift register are ignored, only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied
logic low to disable the DAC Registers.
Table V.Address Decode
AD5544/AD5554
AD5544/AD5554 PIN FUNCTION DESCRIPTIONS
3VREFA
4RFBA
AD5544/AD5554 PIN CONFIGURATION

Partno	Mfg	Dc	Qty	Available	Descript
AD5544		N/a	2	avai	Precision QUAD 16-Bit DAC