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AD5541A
2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-/12-Bit nanoDAC™ in 8-lead 3 mm 脳 3 mm LFCSP
ANALOG
DEVICES
2.7 ll to 5.5 ll, Serial-lnput,
Voltage Output, Unhuffered 16-Bit Mil
AD5541A
FEATU RES
16-bit resolution
11.8 nv/o/Hz noise spectral density
q us settling time
1.1 nV-sec glitch energy
0.05 ppm/°C temperature drift
5 kV HBM ESD classification
0.375 mW power consumption at 3 V
2.7 V to 5.5 V single-supply operation
Hardware Eand LDAC functions
50 MHz SPl-/QSPl-IMlCROWIRE-lDSP-compatible interface
Power-on reset clears DAC output to zero scale
Available in 3 mm x 3 mm, 8-/10-|ead LFCSP and 10-lead
APPLICATIONS
Automatic test equipment
Precision source-measure instruments
Data acquisition systems
Medical instrumentation
Aerospace instrumentation
Communications infrastructure equipment
Industrial control
GENERAL DESCRIPTION
The AD5541A is a single, 16-bit, serial input, unbuffered voltage
output digital-to-analog converter (DAC) that operates from a
single 2.7 V to 5.5 V supply.
The DAC output range extends from 0 V to VREF and is guaranteed
monotonic, providing i1 LSB INL accuracy at 16 bits without
adjustment over the full specified temperature range of -40oC
to +125°C. The AD5541A is available in a 3 mm X 3 mm, 10-lead
LFCSP and 10-lead MSOP. The AD5541A-1 is available in a
3 mm X 3 mm, 8-lead LFCSP.
Offering unbuffered outputs, the AD5541A achieves a 1 ps set-
tling time with low power consumption and low offset errors.
Providing low noise performance of 11.8 nVNHz and low
glitch, the AD5541A is suitable for deployment across multiple
end systems.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
tesponsibileyisassumed byAnalog Devicesfor its use. nor%ranyinhingementsofpatentsurother
rights of third partiesthat may Iesultfrom itsusa Spedfiotions subject to thangewithout notice No
license is granted by implication or otherwise under any patent or patent rights of Analog Davies.
Trademarks and registered trademarks arethe pmpertyof their respective owners.
FUNCTIONAL BLOCK DIAGRAMS
AD5541A
16-BIT DAC
REF Vou‘r
VLOGIC
16-BIT DAC LATCH
CONTROL
SERIAL INPUT REGISTER
Figure 1.AD5541A
AD5541A-1
REF 16-BIT DAC ) vouT
SERIAL INPUT REGISITER
Figure 2. AD5541A-1
CONTROL
The AD5541A uses a versatile 3-wire interface that is compatible
with 50 MHz SPI, QSPI'", MICROWIRE"', and DSP interface
standards.
Table 1. Related Devices
Part No. Description
ADSO40/AD5060 2.7 V to 5.5 V 14-/16-bit buffed output DACs
AD5541/AD5542 2.7 V to 5.5 V 16-bit voltage output DACs
AD5781/AD5791 18-/20-bit voltage output DACs
AD5024/AD5064 4.5 V to 5.5 V, 12-/16-bit quad channel DACs
AD5061 Single, 16-bit nanoDAC, i4 LSB INL, SOT-23
AD5542A l6-bit, bipolar, voltage output DAC
PRODUCT HIGHLIGHTS
16-bit performance without adjustment.
2.7 V to 5.5 V single operation.
Low 11.8 nV/‘le noise spectral density.
Low 0.05 ppm/°C temperature drift.
3 mm x 3 mm LFCSP and MSOP packaging.
.U‘tPE-“Pl‘
One Technology Way, P.0. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781 .329.4700
Fax: 781.461.3113 ©2010-20q 1 Analog Devices, Inc. All rights reserved.
AD5541A
TABLE OF CONTENTS
Features m............................................................................................. 1
Applications _...................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description P........................................................................ 1
Product Highlights _.......................................................................... 1
Revision History w.............................................................................. 2
Specifications F.................................................................................... 3
AC Characteristics _....................................................................... 4
Timing Characteristics w............................................................... 5
Absolute Maximum Ratings B........................................................... 6
ESD Caution _................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics w............................................ 9
Terminology F................................................................................... 13
Theory of Operation V..................................................................... 14
Digital-to-Analog Section ......................................................... 14
REVISION HISTORY
3/1 l-Rev. 0 to Rev. A
Added 10-Lead LFCSP and 8-Lead LFCSP ..................... Universal
Changes to Features, General Description, and Product
Highlights Sections and Table 1 F.................................................... 1
Added Figure 2; Renumbered Sequentially .................................. 1
Changes to Logic Inputs Parameter, Table 1 ................................. 3
Changes to Figure 3 w......................................................................... 5
Changes to Table 5 w........................................................................... 6
Changes to Table 6 w........................................................................... 7
Serial Interface ............................................................................ 14
Unipolar Output Operation _..................................................... 15
Output Amplifier Selection ....................................................... 15
Force Sense Amplifier Selection w.............................................. 16
Reference and Ground P.............................................................. 16
Power-On Reset w......................................................................... 16
Power Supply and Reference Bypassing .................................. 16
Applications Information w............................................................. 17
Microprocessor Interfacing _...................................................... 17
AD5541A to ADSP-BF531 Interface ....................................... 17
AD5541A to SPORT Interface _................................................. 17
Layout Guidelines ....................................................................... 17
Galvanically Isolated Interface w................................................ 17
Decoding Multiple DACs F......................................................... 18
Outline Dimensions w...................................................................... 19
Ordering Guide w......................................................................... 20
Added Figure 5 and Figure 6 Q........................................................... 8
Added Table 7; Renumbered Sequentially ..................................... 8
Changes to Figure 15 q..................................................................... 10
Changed VREF to VREF - 1 LSB in Unipolar Output Operation
Section B............................................................................................. 15
Updated Outline Dimensions P...................................................... 18
Changes to Ordering Guide w......................................................... 18
7/ IO-Revision 0: Initial Version
Rev. A l Page 2 of 20
AD5541A
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 2.5 V S VREF S VDD, AGND = DGND = 0 V, -40''C < TA < +125°C,l unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Condition
STATIC PERFORMANCE
Resolution 16 Bits
Relative Accuracy (INL) t0.5 :1.0 LSB B grade
t0.5 $2.0 LSB A grade
Differential Nonlinearity (DNL) $0.5 t1.0 LSB Guaranteed monotonic
Gain Error 0.5 t2 LSB TA = 25°C
:3 LSB -40oC < TA < +85°C
i4 LSB -40oC < TA < +125°C
Gain ErrorTemperature Coefficient t0.1 ppm/°C
Zero-Code Error 0.3 to. LSB TA = 25°C
$1.5 LSB -40''C < TA < +85°C
i3 LSB -40''C < TA < +125°C
Zero-Code Temperature Coefficient i005 ppm/°C
DC Power Supply Rejection Ratio tl LSB Ava, i 10%
OUTPUT CHARACTERISTICS,
Output Voltage Range 0 VREF - 1 LSB V Unipolar operation
DAC Output Impedance 6.25 k0 Tolerance typically 20%
DAC REFERENCE INPUT3
Reference Input Range 2.0 Von V
Reference Input Resistance 9 k0 Unipolar operation
Reference Input Capacitance 26 pF Code 0x0000
26 pF Code OxFFFF
LOGIC INPUTS
Input Current tl pA
Input Low Voltage, VINL 0.4 V VLOGIC = 1.8 V to 5.5 V
0.8 V VLOGIC = 2.7 V to 5.5 V
Input High Voltage, VINH 2.4 V VLOGIC = 4.5 V to 5.5 V
1.8 V VLOGIC = 2.7 V to 3.6 V
1.3 V VLOGIC = 1.8 V to 2.7 V
Input Capacitance2 10 pF
Hysteresis Voltage2 0.15 V
POWER REQUIREMENTS
VDD 2.7 5.5 V All digital inputs at 0 V, VLOGIC, orVoo
loo 125 150 pA w, =VLOGIC or Va, and h-- GND
VLOGIC 1 .8 5.5 V
ILOGIC 15 24 pA All digital inputs at 0 V, VLOGIC, or Va,
Power Dissipation 0.625 0.825 mW
l For 2.7 V S VLOGIC S 5.5 V: -40''C < TA < +125''C. For 1.8 V S VLOGIC S 2.7 V: -40oC < T, < +105°C.
2 Guaranteed by design, but not subject to production test.
3 Reference input resistance is code-dependent, minimum at 0x8555.
Rev. A l Page 3 of 20
AD5541A
AC CHARACTERISTICS
Vm, = 2.7 V to 5.5 V, 2.5 V S VREF S Van, AGND = DGND = 0 V, -40oC < TA < +125°C, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Test Condition
Output Voltage Settling Time 1 us To 1/2 LSB of full scale, CL = 10 pF
Slew Rate 17 V/ps CL = 10 pF, measured from 0% to 63%
Digital-to-Analog Glitch Impulse 1.1 nv-sec 1 LSB change around major carry
Reference -3 dB Bandwidth 2.2 MHz All ls loaded
Reference Feedthrough 1 mV p-p All Os loaded, VREF = 1 V p-p at 100 kHz
Digital Feedthrough 0.2 nV-sec
Signal-to-Noise Ratio 92 dB
Spurious Free Dynamic Range 80 dB Digitally generated sine wave at 1 kHz
Total Harmonic Distortion 74 dB DAC code = OxFFFF, frequency 10 kHz,
VREF = 2.5 V i 1 V p-p
Output Noise Spectral Density 11.8 nV/VHz DAC code = 0x0000, frequency = 1 kHz
Output Noise 0.134 pV p-p 0.1 Hz to 10 Hz
Rev. A l Page 4 of 20
AD5541A
TIMING CHARACTERISTICS
Vor, = 5 V, 2.5 V S VREF S Vom VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V, -40oC < TA < +105°C, unless otherwise
noted.
Table 4.
Limit at Limit at
Parameter; 1.8 s VLOGIC s 2.7 V 2.7 V s VLOGIC s 5.5 V Unit Description
fscut 14 50 MHz max SCLK cycle frequency
t, 70 20 ns min SCLK cycle time
t2 35 10 ns min SCLK high time
t3 35 10 ns min SCLK low time
t4 5 5 ns min 3 low to SCLK high setup
ts 5 5 ns min 3 high to SCLK high setup
ts 5 5 ns min SCLK high toalow hold time
t7 10 5 ns min SCLK high tocrshigh hold time
t8 35 10 ns min Data setup time
ts 5 4 ns min Data hold time (VINH = 90% ofVDD, VINL = 10% ofVDD)
ts 5 5 ns min Data hold time (VINH = 3 V, VINL = O V)
t1o 20 20 ns min LD-AC pulse width
tn 10 10 ns min Ehigh tomlow setup
1:12 15 15 ns min 3 high time between active periods
l Guaranteed by design and characterization. Not production tested.
2 All input signals are speciMd with tr, = te = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
SCLK \J L, L/ \J \J lr,
k - - t2 ts J - ts -
t4 tr - n
(ts)(') C)c)c)c)
LDAC J"''] d'
Figure 3. Timing Diagram
Rev. A l Page 5 of 20
AD5541A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
Von to AGND -0.3 V to +6 V
VLOGIC t0 DGND -0.3 V to +6 V
Digital Input Voltage to DGND -0.3 V to VDD/VLOGIC +
VOUT to AGND -0.3 V to VDD + 0.3 V
AGND to DGND -0.3 V to +0.3 V
Input Current to Any Pin Except Supplies :10 mA
Operating Temperature Range
Industrial (A, B Versions) -40oC to +125°C
Storage Temperature Range -65°C to +150°C
Maximum Junction Temperature (T, max) 150°C
Package Power Dissipation
Thermal Impedance, eJA
LFCSP (CP-IO-S)
LFCSP (CP-8-1 1)
MSOP (RM-10)
Lead Temperature, Soldering
PeakTemperaturel
(T, max - TAVGJA
50°C/W
62°C/W
1 35°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
l As per JEDEC Standard 20.
2 Human body model (HBM) classification.
Rev. A l Page 6 of 20
AD5541A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD l . m VLOGIC
Vow n AD5541A s_s DGND
AGND s TOP VIEW ts LDAC
REF u (Notto Scale) DIN
trs s n SCLK
Figure 4. ADS541A IO-Lead MSOP Pin Configuration
Table 6. AD5541A Pin Function Descriptions
Pin No. Mnemonic Description
1 Von Analog Supply Voltage.
2 Your Analog Output Voltage from the DAC.
3 AGND Ground Reference Point for Analog Circuitry.
4 REF Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. The reference can range from
2 V to V00.
5 6 Logic Input Signal. The chip select signal is used to frame the serial data input.
6 SCLK Clock Input. Data is clocked into the serial input register on the rising edge of SCLK. The duty cycle must be
between 40% and 60%.
7 DIN Serial Data Input. This device accepts l6-bit words. Data is clocked into the serial input register on the rising edge
of SCLK.
8 m LD-AC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
serial register data.
9 DGND Digital Ground. Ground reference for digital circuitry.
10 VLOGIC Logic Power Supply.
Rev. A l Page 7 of 20
AD5541A
v 1 n C
REF 1 II E 8 GND DD - T 10 VLOG'C
- VOUT 2 Ci AD5541A L- 9 DGND
cs 2 J A05541A-1 C 7 Von AGND 3 3 TOP VIEW E 8 LD-AC
TOP VIEW C - (Not to Scale) r-
SCLK 3 3 (None Scale) 6 Vour REF 4 _- L 1 DIN
DIN4I| E5CLR (7553 C6 SCLK
1. FOR INCREASED RELIABILITY OF THE SOLDER
JOINTS AND MAXIMUM THERMAL CAPABILITY,
IT IS RECOMMENDED THAT THE PAD BE SOLDERED
1. FOR INCREASED RELIABILITY OF THE SOLDER
JOINTS AND MAXIMUM THERMAL CAPABILITY,
IT IS RECOMMENDED THAT THE PAD BE SOLDERED
TO THE SUBSTRATE, GND.
Figure 5. ADSS41A- I 8-Lead LFCSP Pin Configuration
TO THE SUBSTRATE, GND.
Figure 6. AD5541A IO-Lead LFCSP Pin Configuration
Table 7. AD5541A-1 and AD5541A Pin Function Descriptions
Pin No.
8-Lead LFCSP 10-Lead LFCSP Mnemonic Description
1 4 REF Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. The
reference can range from 2 V to Von.
2 5 6 Logic Input Signal. The chip select signal is used to frame the serial data input.
3 6 SCLK Clock Input. Data is clocked into the serial input register on the rising edge of SCLK.
Duty cycle must be between 40% and 60%.
4 7 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the serial input
register on the rising edge of SCLK.
5 N/A1 fl Asynchronous aearinput.ThectRinput is falling edge sensitive. WhenctRis low, all
LDAC pulses are ignored. When a is activated, the serial input register and the DAC
register are cleared to zero scale.
6 2 Vow Analog Output Voltage from the DAC.
N/A1 9 DGND Digital Ground. Ground reference for digital circuitry.
7 1 Von Analog Supply Voltage.
8 N/A1 GND Ground Reference Point for Both Analog and Digital Circuitry.
N/A1 3 AGND Ground Reference Point for Analog Circuitry.
N/A1 10 VLOGIC Logic Power Supply.
N/A1 8 LDAC LD-AC Input. When this input is taken low, the DAC register is simultaneously updated
with the contents ofthe serial input register.
EPAD Exposed Pad. For increased reliability ofthe solderjoints and maximum thermal
capability, it is recommended that the pad be soldered to the substrate, GND.
l N/A means not applicable.
Rev. A l Page 8 of 20
AD5541A
TYPICAL PERFORMANCE CHARACTERISTICS
0.50 I 0.50 I
VDD = 5V VDD = 5V
VREF = 2.5V 5 VREF = 2.5V
g 0.25 =L
:L F 0.25
g o I I ' 1 . g
Ul - M hh W
g 5 o H 410mm
g -0 25 d 5
I l ' S l
t' n I l - r (I 'l' Iti Ivhttt t
E 5 -0.25 I
E -th50 " I I I lt
-0-75 g -0.50 g
0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 3 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 3
CODE ' CODE t'az'i',r
Figure 7. Integral Nonlinearity vs. Code Figure 10. Differential Nonlinearity vs. Code
0.25 I I 0.75 I I
VDD = 5V VDD = 5V
VREF = 2.5V A VREF = 2.5V
[is," 0 ',1 0.50
F L- "ss.
L- ttt _
ttt E "s..
< -0.25 a 0.25
m ""-..... - "s,
a "-----....., -l "ss,
D 'ss g
5 -0.50 a' 0 "ss
g "s, 5 "ss
'r, Ah75 [t -th25
M.00 5 -0.50 e
-60 -40 -20 0 20 40 60 80 100 120 140 g -60 -40 -20 0 20 40 60 80 100 120 140 g
TEMPERATURE (°C) Fa',, TEMPERATURE (°C) 'il
Figure 8. Integral Nonlinearity vs. Temperature Figure 1 1. Differential Nonlinearity vs. Temperature
0.50 I 0.75 I
VREF = 2.5V VDD = 5V
TA = 25'C TA = 25''C
0 25 -"---- 0.50
A DNL A DNL
m n: "'''s,
o 0 o 0.25 -_.
ttt ttt
Ill IU
E Ah25 E 0
ff, f,
a ce INL --'"'"ss
15 3 "ss,
-0 50 "s. Al 25
-0.75 g -0.50 :
2 3 4 5 6 7 g o 1 2 3 4 5 6 g
SUPPLY VOLTAGE (V) rv,s',,t REFERENCE VOLTAGE (V) [ii
Figure 9. Linearity Error vs. Supply Voltage
Rev. A l Page 9 of 20
Figure 12. Linearity Error vs. Reference Voltage
