AD5541 Fast Delivery |IC PHOENIX CO.,LIMITED

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AD5541
16-Bit Voltage-Output DAC in SO-8 Package
REV.A
5 V, Serial-Input
Voltage-Output, 16-Bit DACs
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Full 16-Bit Performance
5 V Single Supply Operation
Low Power
Short Settling Time
Unbuffered Voltage Output Capable of Driving 60kV
Loads Directly
SPI™/QSPI™/MICROWIRE™-Compatible Interface
Standards
Power-On Reset Clears DAC Output to 0 V (Unipolar
Mode)
Schmitt Trigger Inputs for Direct Optocoupler Interface
APPLICATIONS
Digital Gain and Offset Adjustment
Automatic Test Equipment
Data Acquisition Systems
Industrial Process Control
GENERAL DESCRIPTION
The AD5541 and AD5542 are single, 16-bit, serial input,
voltage output DACs that operate from a single 5 V – 10%
supply.
The AD5541 and AD5542 utilize a versatile 3-wire interface that
is compatible with SPI, QSPI, MICROWIRE, and DSP inter-
face standards.
These DACs provide 16-bit performance without any adjust-
ments. The DAC output is unbuffered, which reduces power
consumption and offset errors contributed to by an output buffer.
The AD5542 can be operated in bipolar mode generating aVREF output swing. The AD5542 also includes Kelvin sense
connections for the reference and analog ground pins to reduce
layout sensitivity.
The AD5541 and AD5542 are available in an SO package.
PRODUCT HIGHLIGHTSSingle Supply Operation.
The AD5541 and AD5542 are fully speciﬁed and guaranteed
for a single 5 V – 10% supply.Low Power Consumption.
These parts consume typically 1.5 mW with a 5 V supply.3-Wire Serial Interface.Unbuffered output capable of driving 60kW loads.
This reduces power consumption as there is no internal buffer
to drive.Power-On Reset circuitry.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
AD5541/AD5542–SPECIFICATIONS
AD5542
OUTPUT CHARACTERISTICS
DAC REFERENCE INPUT
REFERENCE
POWER REQUIREMENTS
NOTESTemperature ranges are as follows: A, B, C Versions: –40°C to +85°C. J, L Versions: 0°C to 70°C.Reference input resistance is code-dependent, minimum at 8555 hex.Guaranteed by design, not subject to production test.
Speciﬁcations subject to change without notice.
(VDD = 5 V 6 10%, VREF = 2.5 V, AGND = DGND = 0 V. All speciﬁcations
TA = TMIN to TMAX, unless otherwise noted.)
DIN
LDAC*
*AD5542 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
Figure 1.Timing Diagram
TIMING CHARACTERISTICS1, 2
t10
t11
(VDD = 5 V 6 5%, VREF = 2.5 V, AGND = DGND = 0 V. All speciﬁcations TA = TMIN to TMAX, unless
otherwise noted.)
AD5541/AD5542
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5541/AD5542 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
AGND, AGNDF, AGNDS to DGND . . . . . –0.3 V to +0.3 V
Input Current to Any Pin Except Supplies . . . . . . . . –10 mA
Operating Temperature Range
Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C
Commercial (J, L Versions) . . . . . . . . . . . . . . . 0°C to 70°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
ORDERING GUIDE
Die Size = 80 · 139 = 11,120 sq mil; Number of Transistors = 1,230.
Maximum Junction Temperature, (TJ max) . . . . . . . . . 150°C
Package Power Dissipation . . . . . . . . . . . . .(TJ max – TA)/qJA
Thermal Impedance qJA
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . 149.5°C/W
SOIC (R-14) . . . . . . . . . . . . . . . . . . . . . . . . . . 104.5°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD5541 PIN FUNCTION DESCRIPTIONS
AD5542 PIN FUNCTION DESCRIPTIONS
AD5541 PIN CONFIGURATION
SOIC
VOUT
AGND
REF
VDD
DGND
DIN
SCLKCS
AD5542 PIN CONFIGURATION
SOIC
AD5541/AD5542
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL versus code plot can be seen in Figure 2.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A speciﬁed differential nonlinearity of –1 LSB maximum
ensures monotonicity. Figure 3 illustrates a typical DNL versus
code plot.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range.
It is the deviation in slope of the DAC transfer characteristic
from ideal.
Gain Error Temperature Coefficient
This is a measure of the change in gain error with changes in
temperature. It is expressed in ppm/°C.
Zero Code Error
Zero code error is a measure of the output error when zero code
is loaded to the DAC register.
Zero Code Temperature Coefﬁcient
This is a measure of the change in zero code error with a change
in temperature. It is expressed in mV/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally speciﬁed as the area of the glitch in nV-s
and is measured when the digital input code is changed by 1LSB
at the major carry transition. A plot of the glitch impulse is shown
in Figure 15.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. CS is
held high, while the CLK and DIN signals are toggled. It is
speciﬁed in nV-s and is measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa. A typi-
cal plot of digital feedthrough is shown in Figure 14.
Power Supply Rejection Ratio
This speciﬁcation indicates how the output of the DAC is affected
by changes in the power supply voltage. Power-supply rejection
ratio is quoted in terms of % change in output per % change in
VDD for full-scale output of the DAC. VDD is varied by –10%.
Reference Feedthrough
This is a measure of the feedthrough from the VREF input to the
DAC output when the DAC is loaded with all 0s. A 100 kHz,V p-p is applied to VREF. Reference feedthrough is expressed
in mV p-p.

Partno	Mfg	Dc	Qty	Available	Descript
AD5541	AD	N/a	190	avai	16-Bit Voltage-Output DAC in SO-8 Package