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AD5533BBC-1
32-Channel Infinite Sample-and-Hold
REV.A
32-Channel Precision
Infinite Sample-and-Hold
FEATURES
Infinite Sample-and-Hold Capability to �0.018% Accuracy
Infinite Sample-and-Hold Total Unadjusted Error �2.5mV
High Integration:
32-Channel DAC in 12 mm � 12 mm CSPBGA
Per Channel Acquisition Time of 16 �s Max
Adjustable Voltage Output Range
Output Impedance 0.5�
Output Voltage Span 10 V
Readback Capability
DSP/Microcontroller Compatible Serial Interface
Parallel Interface
Temperature Range –40�C to +85�C
APPLICATIONS
Optical Networks
Automatic Test Equipment
Level Setting
Instrumentation
Industrial Control Systems
Data Acquisition
Low Cost I/O
FUNCTIONAL BLOCK DIAGRAM
SYNC/CS
CALA4–A0SCLKOFFSET
DVCC
VIN
DINDOUT
AVCCREFREFOFFSIN
OFFSOUT
VOUT 31
VOUT 0
TRACK/RESET
BUSY
DAC
AGND
DGND
SER/ PAR
VDDVSS
GENERAL DESCRIPTIONThe AD5533B combines a 32-channel voltage translation function
with an infinite output hold capability. An analog input voltage on
the common input pin, VIN, is sampled and its digital represen-
tation transferred to a chosen DAC register. VOUT for this DAC
is then updated to reflect the new contents of the DAC register.
Channel selection is accomplished via the parallel address inputs
A0–A4 or via the serial input port. The output voltage range is
determined by the offset voltage at the OFFS_IN pin and the gain
of the output amplifier. It is restricted to a range from VSS + 2V
to VDD – 2 V because of the headroom of the output amplifier.
The device is operated with AVCC = +5V ± 5%, DVCC = +2.7V
to +5.25V, VSS = –4.75V to –16.5 V, and VDD = +8 V to
+16.5V and requires a stable 3V reference on REF_IN as well
as an offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTSPrecision infinite droopless sample-and-hold capability.The AD5533B is available in a 74-lead CSPBGA with a
body size of 12 mm � 12 mm.In infinite sample-and-hold mode, a total unadjusted error of
±2.5 mV is achieved by laser-trimming on-chip resistors.
*. Patent No. 5,969,657; other patents pending.
AD5533B–SPECIFICATIONS
(VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V;
DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFFS_IN = 0 V;
Output Range from VSS + 2 V to VDD – 2 V. All outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.)ANALOG CHANNEL
AD5533BNOTES
1See Terminology section.
2B Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
3Guaranteed by design and characterization, not production tested.
4AD780 as reference for the AD5533B.
5Ensure that you do not exceed TJ (max). See Absolute Maximum Ratings.
6Outputs unloaded.
Specifications subject to change without notice.
AC CHARACTERISTICS
(VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V; DVCC = +2.7 V to +5.25 V;
AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFFS_IN = 0 V; Output Range from VSS + 2 V to VDD – 2 V.
All outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.)Output Settling Time
Acquisition Time
OFFS_IN Settling Time
NOTES
1B version: Industrial temperature range –40°C to +85°C; typical at 25°C.
2Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
AD5533B
TIMING CHARACTERISTICS
PARALLEL INTERFACENOTESSee Parallel Interface Timing Diagram.Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACEt10
NOTESSee Serial Interface Timing Diagrams.Guaranteed by design and characterization, not production tested.These numbers are measured with the load circuit of Figure 2.SYNC should be taken low while SCLK is low for readback.
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAMFigure 1.Parallel Write (ISHA Mode Only)
Figure 2.Load Circuit for DOUT Timing Specifications
SERIAL INTERFACE TIMING DIAGRAMSFigure 3.10-Bit Write (ISHA Mode and Both Readback Modes)
Figure 4.14-Bit Read (Both Readback Modes)
AD5533B
ORDERING GUIDE*Separate Data Sheet
ABSOLUTE MAXIMUM RATINGS1, 2(TA = 25°C, unless otherwise noted.)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AVCC to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVCC + 0.3 V
Digital Outputs to DGND . . . . . . . . . –0.3 V to DVCC + 0.3 V
REF_IN to AGND, DAC_GND . . . .–0.3 V to AVCC + 0.3 V
VIN to AGND, DAC_GND . . . . . . . . –0.3 V to AVCC + 0.3 V
VOUT0–31 to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
OFFS_IN to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
OFFS_OUT to AGND . . . . AGND – 0.3 V to AVCC + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C
74-Lead CSPBGA Package, θJA Thermal Impedance . . 41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
Max Power Dissipation . . . . . . . . . . . . (150°C – TA)/θJA mW3
Max Continuous Load Current at TJ = 70°C,
per Channel Group . . . . . . . . . . . . . . . . . . . . . . . 15.5 mA4
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
3This limit includes load power.
4This maximum allowed continuous load current is spread over eight channels,
with channels grouped as follows:
Group 1: Channels 3, 4, 5, 6, 7, 8, 9, 10
Group 2: Channels 14, 16, 18, 20, 21, 24, 25, 26
Group 3: Channels 15, 17, 19, 22, 23, 27, 28, 29
Group 4: Channels 0, 1, 2, 11, 12, 13, 30, 31
For higher junction temperatures, derate as follows:
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5533B features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION34567891011
74-Lead CSPBGA Ball ConfigurationA10
A11
*NC = Not Connected
AD5533B
PIN FUNCTION DESCRIPTIONSNOTESInternal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
