AD5533ABC-1 Fast Delivery |IC PHOENIX CO.,LIMITED

AD5533ABC-1 ,32-Channel, 14-Bit Voltage-Output DACspecifications TSS DD MINto T unless otherwise noted.)MAX2 A Version Conditions ..
AD5533BBC-1 ,32-Channel Infinite Sample-and-Holdspecifications T to T , unless otherwise noted.)SS DD MIN MAX1 2Parameter B Version Unit Conditions ..
AD5539JQ , Ultrahigh Frequency Operational Amplifier
AD5541 ,16-Bit Voltage-Output DAC in SO-8 PackageGENERAL DESCRIPTIONCS16-BIT DATA LATCHThe AD5541 and AD5542 are single, 16-bit, serial input,LDACCO ..
AD5541A ,2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-/12-Bit nanoDAC™ in 8-lead 3 mm 脳 3 mm LFCSPGENERAL DESCRIPTION with 50 MHz SPI, QSPI, MICROWIRE, and DSP interface The AD5541A is a single, ..
AD5541AR ,5 V, Serial-Input Voltage-Output, 16-Bit DACsAPPLICATIONSDigital Gain and Offset AdjustmentDGNDAutomatic Test EquipmentVDDData Acquisition Syste ..
AD9631AR ,Ultralow Distortion, Wide Bandwidth Voltage Feedback Op AmpsCHARACTERISTICSOutput Voltage Range, R = 150 Ω±3.2 ±3.9 ±3.2 ±3.9 VLOutput Current 70 70 mAOutput R ..
AD9631AR-REEL , Ultralow Distortion, Wide Bandwidth Voltage Feedback Op Amps
AD9632 ,Ultralow Distortion, High Speed Op Amp, Stable at Gain of 2Specifications subject to change without notice.–2– REV. BAD9631/AD96321ABSOLUTE MAXIMUM RATINGS MA ..
AD9632AN ,Ultralow Distortion, Wide Bandwidth Voltage Feedback Op AmpsCHARACTERISTICSInput Resistance 500 500 kΩInput Capacitance 1.2 1.2 pFInput Common-Mode Voltage Ran ..
AD9632AR ,Ultralow Distortion, Wide Bandwidth Voltage Feedback Op AmpsFEATURESFUNCTIONAL BLOCK DIAGRAMWide Bandwidth AD9631, G = +1 AD9632, G = +28-Pin Plastic Mini-DIP ..
AD9640ABCPZ-80 , 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter

AD5533ABC-1
32-Channel, 14-Bit Voltage-Output DAC
REV.0
32-Channel, 14-Bit
Voltage-Output DAC
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD5532 is a 32-channel voltage-output 14-bit DAC with
an additional infinite sample-and-hold mode. The selected DAC
register is written to via the 3-wire serial interface and VOUT
for this DAC is then updated to reflect the new contents of the
DAC register. DAC selection is accomplished via address bits
A0–A4. The output voltage range is determined by the offset
voltage at the OFFS_IN pin and the gain of the output amplifier.
It is restricted to a range from VSS + 2 V to VDD – 2 V because
of the headroom of the output amplifier.
The device is operated with AVCC = 5 V ± 5%, DVCC = 2.7 V
to 5.25 V, VSS = –4.75 V to –16.5 V and VDD = 8 V to 16.5 V
and requires a stable +3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS32-channel, 14-bit DAC in one package, guaranteed
monotonic.The AD5532 is available in a 74-lead LFBGA package with
a body size of 12 mm × 12 mm.Droopless/Infinite Sample-and-Hold Mode.
FEATURES
High Integration: 32-Channel DAC in 12 � 12 mm2 LFBGA
Adjustable Voltage Output Range
Guaranteed Monotonic
Readback Capability
DSP-/Microcontroller-Compatible Serial Interface
Output Impedance
0.5 � (AD5532-1, AD5532-2)
500 � (AD5532-3)
1 k� (AD5532-5)
Output Voltage Span
10 V (AD5532-1, AD5532-3, AD5532-5)
20 V (AD5532-2)
Infinite Sample-and-Hold Capability to �0.018% Accuracy
Temperature Range –40�C to +85�C
APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
Low Cost I/O
*. Patent No. 5,969,657; other patents pending.
AD5532–SPECIFICATIONS(VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to
5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from VSS + 2 V to VDD – 2 V. All outputs unloaded. All specifications TMIN
to TMAX unless otherwise noted.)
AD5532
POWER REQUIREMENTS
AC CHARACTERISTICSGuaranteed by design and characterization, not production tested.AD780 as reference for the AD5532.
SHA MODE
ANALOG CHANNEL
ANALOG INPUT (OFFS_IN)
NOTESSee Terminology.
Specifications subject to change without notice.
AD5532
TIMING CHARACTERISTICS
PARALLEL INTERFACE
NOTESSee Interface Timing Diagram.Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACE
NOTESSee Serial Interface Timing Diagrams.Guaranteed by design and characterization, not production tested.In SHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.These numbers are measured with the load circuit of Figure 2.
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAMS
Figure 1.Parallel Write (SHA Mode Only)
Figure 2.Load Circuit for DOUT Timing Specifications
SERIAL INTERFACE TIMING DIAGRAMS
Figure 3.10-Bit Write (SHA Mode and Both Readback Modes)
Figure 4.24-Bit Write (DAC Mode)
Figure 5.14-Bit Read (Both Readback Modes)
AD5532
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AVCC to AGND, DAC_GND . . . . . . . . . . . . .–0.3 V to +7 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVCC + 0.3 V
Digital Outputs to DGND . . . . . . . . . –0.3 V to DVCC + 0.3 V
REF_IN to AGND, DAC_ GND . . . . . . . . . . –0.3 V to +7 V
VIN to AGND, DAC_GND . . . . . . . . . . . . . . . –0.3 V to +7 V
VOUT0–31 to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
VOUT0–31 to VSS . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +24 V
OFFS_IN to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
OFFS_OUT to AGND . . . . AGND – 0.3 V to AVCC + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C
74-Lead LFBGA Package, θJA Thermal Impedance . . . 41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
*Separate Data Sheet.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5532 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION234567891011234567891011
74-Lead LFBGA Ball Configuration
AD5532
PIN FUNCTION DESCRIPTION
NOTESInternal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
2.963V70mV0V
VOUT
VIN
IDEAL TRANSFER
FUNCTION
IDEAL GAIN � REFIN
OUTPUT
VOLTAGE
IDEAL GAIN � 50mV16k
FULL-SCALE
ERROR RANGE
OFFSET
RANGE

Partno	Mfg	Dc	Qty	Available	Descript
AD5533ABC-1 \|AD5533ABC1	ADI	N/a	2	avai	32-Channel, 14-Bit Voltage-Output DAC