AD5532HSABC Fast Delivery |IC PHOENIX CO.,LIMITED

AD5532HSABC ,32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interfacespecifications T to T unless otherwise noted.)MIN MAX2 A Version1Parameter Min Typ M ..
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AD5532HSABC
32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interface
REV.0
32-Channel 14-Bit DAC with
High-Speed 3-Wire Serial Interface
FUNCTIONAL BLOCK DIAGRAM
VDDVSS
VOUT0
VOUT1
VOUT30
VOUT31RESET
DAC_GND
AGND
DGND
DVCCAVCCREF_INOFFS_IN
DINSCLKSYNC
FEATURES
High Integration: 32-Channel DAC in 12 � 12 mm2 LFBGA
Guaranteed Monotonic
DSP-/Microcontroller-Compatible Serial Interface
Channel Update Rate 1.1 MHz
Output Impedance 0.5 �
Selectable Output Voltage 0 V to 5 V or –2.5 V to +2.5 V
Asynchronous RESET Facility
Temperature Range –40�C to +85�C
APPLICATIONS
Optical Networks
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
Low Cost I/O
GENERAL DESCRIPTION
The AD5532HS is a 32-channel voltage-output 14-bit DAC
with a high-speed serial interface. The selected DAC register is
written to via the 3-wire interface. The serial interface operates
at clock rates up to 30 MHz and is compatible with DSP and
microcontroller interface standards. The output voltage range is
0 V to 5 V or –2.5 V to +2.5 V and is determined by the offset
voltage at the OFFS_IN pin. It is restricted to a range from
VSS + 2 V to VDD – 2 V because of the headroom of the out-
put amplifier.
The device is operated with AVCC = 5 V ± 5%, DVCC = 2.7 V
to 5.25 V, VSS = –4.75 V to –12 V and VDD = +4.75 V to +12 V
and requires a stable 2.5 V reference on REF_IN.
PRODUCT HIGHLIGHTS32 14-bit DACs in one package, guaranteed monotonic.The AD5532HS is available in a 74-ball LFBGA package
with a body size of 12 mm by 12 mm.
*. Patent No. 5,969,657; other patents pending.
AD5532HS–SPECIFICATIONS
(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN =
2.5V; OFFS_IN = 0 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
DIGITAL INPUTS
NOTESSee TerminologyA Version: Industrial temperature range –40°C to +85°C; typical at 25°C.Guaranteed by design and characterization, not production tested.Output range is restricted from VSS + 2 V to VDD – 2 V.AD780 as reference for the AD5532HS.Outputs unloaded.
Specifications subject to change without notice.
AD5532HS
(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND =
DGND = DAC_GND = 0 V; REF_IN = 2.5 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
Output Voltage Settling Time
NOTESSee TerminologyGuaranteed by design and characterization, not production testedB Version: Industrial temperature range –40°C to +85°C.Timed from the end of a write sequence.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
NOTESSee Timing Diagrams in Figure 1.Guaranteed by design and characterization, not production tested.All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
AC CHARACTERISTICS
(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;
AGND = DGND = DAC_GND = 0 V; All specifications TMIN to TMAX unless otherwise noted.)
Figure 1. Serial Interface Timing Diagram
AD5532HS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5532HS features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AVCC to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVCC + 0.3 V
REF_IN to AGND, DAC_GND . . . . . . . . . . . –0.3 V to +7 V
VOUT0–VOUT31 to AGND . . . . . . . VSS – 0.3 V to VDD + 0.3 V
VOUT0–VOUT31 to VSS . . . . . . . . . . . . . . . . . . –0.3 V to +24 V
OFFS_IN to AGND . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C
74-Lead LFBGA Package, θJA Thermal Impedance . . . 41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
Max Power Dissipation at TA = 70°C,
Outputs Loaded . . . . . . . . . . . . . . . . . . . . . . . . . . 550mW3
(for TA > 70°C, derate at 26 mW for each °C over 70°C)
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.This limit includes load power and applies only when there is a resistive load on
VOUT outputs.
ORDERING GUIDE
OUTPUT V
DAC CODE
OFFSET
ERROR
16k0
Figure 2.DAC Transfer Function (OFFS_IN = 0)
PIN CONFIGURATION
TOP VIEW
AD5532HS 74-Ball (LFBGA) Configuration
AD5532HS
PIN FUNCTION DESCRIPTIONS
VSS (1–4)
DAC_GND (1–2)
REF_IN
VOUT0–VOUT31
SCLK*
DIN*
OFFS_IN
*Internal pull-up device on this logic input. Therefore, it can be left floating and will default to a logic high condition.
TERMINOLOGY
Integral Nonlinearity (INL)
A measure of the maximum deviation from a straight line pass-
ing through the endpoints of the DAC transfer function. It is
expressed as a percentage of full-scale range.
Differential Nonlinearity (DNL)
The difference between the measured change and the ideal 1 LSB
change between any two adjacent codes. A specified DNL of1 LSB maximum ensures monotonicity.
Offset Error
A measure of the error present at the device output with all 0s
loaded to the DAC. It includes the offset of the DAC and the
output amplifier. It is expressed in mV.
Full-Scale Error
A measure of the output error with all 1s loaded to the DAC.
Ideally the output should be 2 REF_IN if OFFS_IN = 0. It is
expressed as a percentage of full-scale range.
DC Power-Supply Rejection Ratio (PSRR)
A measure of the change in analog output for a change in supply
voltage (VDD and VSS). It is expressed in dB. VDD and VSS are
varied ±5%.
DC Crosstalk
The dc change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of all other DACs. It is expressed in µV.
Output Temperature Coefficient
A measure of the change in analog output with changes in tem-
perature. It is expressed in ppm/°C.
Output Voltage Settling Time
The time taken from when the last data bit is clocked into the
DAC until the output has settled to within ±0.5 LSB of its
final value.
Digital-to-Analog Glitch Impulse
The area of the glitch injected into the analog output when
the code in the DAC register changes state. It is specified as
the area of the glitch in nV-secs when the digital code is changed
by 1 LSB at the major carry transition (011...11 to 100...00
or 100...00 to 011...11).
Digital Crosstalk
The glitch impulse transferred to the output of one DAC at
midscale while a full-scale code change (all 1s to all 0s and vice
versa) is being written to another DAC. It is expressed in nV-secs.
Analog Crosstalk
The area of the glitch transferred to the output (VOUT) of one
DAC due to a full-scale change in the output (VOUT) of another
DAC. The area of the glitch is expressed in nV-secs.
Digital Feedthrough
A measure of the impulse injected into the analog outputs from the
digital control inputs when the part is not being written to, i.e.,
SYNC is high. It is specified in nV-secs and measured with a
worst-case change on the digital input pins, e.g., from all 0s
to all 1s and vice versa.
Output Noise Spectral Density
A measure of internally generated random noise. Random noise is
characterized as a spectral density (voltage per root Hertz). It is
measured by loading all DACs to midscale and measuring
noise at the output. It is measured in nV/√Hz.

Partno	Mfg	Dc	Qty	Available	Descript
AD5532HSABC	ADI	N/a	5	avai	32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interface