AD5532ABC-2 ,32-Channel Infinite Sample-and-Hold32-Channel InfiniteaSample-and-HoldAD5533*
AD5532ABC-5 ,32-Channel Infinite Sample-and-HoldAPPLICATIONSThe device is operated with AV = 5 V ± 5%, DV = 2.7 V toCC CCLevel Setting5.25 V, V = – ..
AD5532ABC-5 ,32-Channel Infinite Sample-and-HoldSPECIFICATIONSto 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range fromV + 2 V to V – ..
AD5532BBC-1 ,32-Channel 14-bit Bipolar Voltage-Output DACspecifications T to T , unless otherwise noted.)SS DD MIN MAXAD5532B-11 2Parameter B Version Unit C ..
AD5532HSABC ,32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interfacespecifications T to T unless otherwise noted.)MIN MAX2 A Version1Parameter Min Typ M ..
AD5533ABC-1 ,32-Channel, 14-Bit Voltage-Output DACspecifications TSS DD MINto T unless otherwise noted.)MAX2 A Version Conditions ..
AD9627BCPZ-125 , 12-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
AD9630AN ,Low Distortion 750 MHz Closed-Loop Buffer AmpSPECIFICATIONSOutput Offset Voltage +25
AD5532ABC-1-AD5532ABC-2-AD5532ABC-5
32-Channel Infinite Sample-and-Hold
REV.0
*. Patent No. 5,969,657; other patents pending.
32-Channel Infinite
Sample-and-Hold
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Infinite Sample-and-Hold Capability to �0.018% Accuracy
High Integration: 32-Channel SHA in 12 � 12 mm2 LFBGA
Per Channel Acquisition Time of 16 �s max
Adjustable Voltage Output Range
Output Voltage Span 10 V
Output Impedance 0.5 �
Readback Capability
DSP-/Microcontroller-Compatible Serial Interface
Parallel Interface
Temperature Range –40�C to +85�C
APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
Low Cost I/O
GENERAL DESCRIPTIONThe AD5533 combines a 32-channel voltage translation function
with an infinite output hold capability. An analog input voltage
on the common input pin, VIN, is sampled and its digital repre-
sentation transferred to a chosen DAC register. VOUT for this
DAC is then updated to reflect the new contents of the DAC
register. Channel selection is accomplished via the parallel address
inputs A0–A4 or via the serial input port. The output voltage
range is determined by the offset voltage at the OFFS_IN pin
and the gain of the output amplifier. It is restricted to a range
from VSS + 2 V to VDD – 2 V because of the headroom of the
output amplifier.
The device is operated with AVCC = 5 V ± 5%, DVCC = 2.7 V to
5.25 V, VSS = –4.75 V to –16.5 V and VDD = 8 V to 16.5 V and
requires a stable 3 V reference on REF_IN as well as an offset
voltage on OFFS_IN.
PRODUCT HIGHLIGHTS1. Infinite Droopless Sample-and-Hold Capability.
2. The AD5533 is available in a 74-lead LFBGA package with a
body size of 12 mm × 12 mm.
AD5533–SPECIFICATIONS
(VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V
to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from
VSS + 2 V to VDD – 2 V. All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)ANALOG CHANNEL
AD5533
(VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND =
DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from VSS + 2 V to VDD – 2 V. All outputs unloaded.
All specifications TMIN to TMAX unless otherwise noted.)Output Settling Time
Acquisition Time
OFFS_IN Settling Time
NOTESA version: Industrial temperature range –40°C to +85°C; typical at 25°C.Guaranteed by design and characterization, not production tested
Specifications subject to change without notice.
POWER REQUIREMENTS
NOTESSee Terminology.A Version: Industrial temperature range –40°C to +85°C; typical at +25°C.Guaranteed by design and characterization, not production tested.AD780 as reference for the AD5533.Ensure that you do not exceed TJ (max). See maximum ratings.Outputs unloaded.
Specifications subject to change without notice.
AC CHARACTERISTICS
AD5533
TIMING CHARACTERISTICS
PARALLEL INTERFACENOTESSee Interface Timing Diagram.Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACENOTESSee Serial Interface Timing Diagrams.Guaranteed by design and characterization, not production tested.These numbers are measured with the load circuit of Figure 2.
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAMFigure 1.Parallel Write (SHA Mode Only)
Figure 2.Load Circuit for DOUT Timing Specifications
SERIAL INTERFACE TIMING DIAGRAMSFigure 3.10-Bit Write (SHA Mode and Both Readback Modes)
Figure 4.14-Bit Read (Both Readback Modes)
AD5533
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5533 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1, 2(TA = 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AVCC to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVCC + 0.3 V
Digital Outputs to DGND . . . . . . . . . –0.3 V to DVCC + 0.3 V
REF_IN to AGND, DAC_GND . . . . . . . . . . . –0.3 V to +7 V
VIN to AGND, DAC_GND . . . . . . . . . . . . . . . –0.3 V to +7 V
VOUT0–31 to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
VOUT0–31 toVSS . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +24 V
OFFS_IN to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
OFFS_OUT to AGND . . . . AGND – 0.3 V to AVCC + 0.3 V
AGND to DGND. . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C
74-Lead LFBGA Package, θJA Thermal Impedance . . . 41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE*Separate Data Sheet.
PIN CONFIGURATION234567891011234567891011
74-Lead LFBGA Ball Configuration
AD5533
PIN FUNCTION DESCRIPTIONSNOTES
1Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.
2Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
