AD5531BRU Fast Delivery |IC PHOENIX CO.,LIMITED

AD5531BRU ,Serial Input, ±10 V Output Voltage Range, 14-Bit DACAPPLICATIONSenced to the potential at DUTGND. LDAC may be used to updateIndustrial Automationthe ou ..
AD5532ABC-1 ,32-Channel Infinite Sample-and-HoldSPECIFICATIONSto 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range fromV + 2 V to V – ..
AD5532ABC-2 ,32-Channel Infinite Sample-and-Hold32-Channel InﬁniteaSample-and-HoldAD5533*
AD5532ABC-5 ,32-Channel Infinite Sample-and-HoldAPPLICATIONSThe device is operated with AV = 5 V ± 5%, DV = 2.7 V toCC CCLevel Setting5.25 V, V = – ..
AD5532ABC-5 ,32-Channel Infinite Sample-and-HoldSPECIFICATIONSto 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range fromV + 2 V to V – ..
AD5532BBC-1 ,32-Channel 14-bit Bipolar Voltage-Output DACspecifications T to T , unless otherwise noted.)SS DD MIN MAXAD5532B-11 2Parameter B Version Unit C ..
AD9627BCPZ-125 , 12-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
AD9630AN ,Low Distortion 750 MHz Closed-Loop Buffer AmpSPECIFICATIONSOutput Offset Voltage +25

AD5531BRU
Serial Input, ±10 V Output Voltage Range, 12-Bit DAC
REV.0
Serial Input, Voltage Output
12-/14-Bit DACs
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
FEATURES
Pin-Compatible 12- and 14-Bit DACs
Serial Input, Voltage Output
Maximum Output Voltage Range of �10 V
Data Readback
3-Wire Serial Interface
Clear Function to a User-Defined Voltage
Power-Down Function
Serial Data Output for Daisy-Chaining
16-Lead TSSOP Packages
APPLICATIONS
Industrial Automation
Automatic Test Equipment
Process Control
General-Purpose Instrumentation
GENERAL DESCRIPTION
The AD5530 and AD5531 are single 12-/14-bit serial input,
voltage output DACs, respectively.
They utilize a versatile 3-wire interface that is compatible with
SPI™, QSPI™, MICROWIRE™, and DSP interface standards.
Data is presented to the part in the format of a 16-bit serial word.
Serial data is available on the SDO pin for daisy-chaining pur-
poses. Data readback allows the user to read the contents of the
DAC register via the SDO pin.
The DAC output is buffered by a gain of 2 amplifier and refer-
enced to the potential at DUTGND. LDAC may be used to update
the output of the DAC asynchronously. A power-down (PD) pin
allows the DAC to be put into a low power state, and a CLR pin
allows the output to be cleared to a user-defined voltage, the
potential at DUTGND.
The AD5530 and AD5531 are available in 16-lead TSSOP
packages.
FUNCTIONAL BLOCK DIAGRAM
SYNCSCLKGND
VOUT
DUTGND
SDO
VSSVDD
RBEN
LDAC
REFIN
REFAGND
SDIN
CLR
AD5530/AD5531–SPECIFICATIONS1(VDD = +15 V ±10%; VSS = –15 V ±10%; GND = 0 V; RL = 5 kΩ and
CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.)
O/P CHARACTERISTICS
POWER REQUIREMENTS
NOTESTemperature range for B Version: –40°C to +85°C.Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
AD5530/AD5531
POWER REQUIREMENTS
NOTESTemperature range for B Version: –40°C to +85°C.Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS
SPECIFICATIONS1(VDD = +12 V ±10%; VSS = –12 V ±10%; GND = 0 V;
RL = 5 kΩ and CL = 220 pF to GND; TA = TMIN to TMAX, unless otherwise noted.)
(VDD = 10.8 V to 16.5 V, VSS = –10.8 V to –16.5 V; GND = 0 V; RL = 5 kΩ and
CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.)
AD5530/AD5531
(VDD = 10.8 V to 16.5 V, VSS = –10.8 V to –16.5 V; GND = 0 V;
RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.)
Figure 1.Timing Diagram for Standalone Mode
STANDALONE TIMING CHARACTERISTICS1, 2
fMAX
1Guaranteed by design. Not production tested.
2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5ns
(10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.
Specifications subject to change without notice.
Figure 2.Timing Diagram for Daisy-Chaining and READBACK Mode
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS1, 2, 3
fMAX
t12
t14
t15
1Guaranteed by design. Not production tested.
2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5ns
(10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.
3SDO; RPULLUP = 5 kΩ, CL = 15 pF.
Specifications subject to change without notice.
(VDD = 10.8 V to 16.5 V, VSS = –10.8V
to –16.5 V; VSS = –15 V ±10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.)
AD5530/AD5531
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5530/AD5531 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
*RU = Thin Shrink Small Outline Package.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V, –17 V
Digital Inputs to GND . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
SDO to GND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6.5 V
REFIN to REFAGND . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
REFIN to GND . . . . . . . . . . . . . . . .VSS – 0.3 V, VDD +0.3 V
REFAGND to GND . . . . . . . . . . . . .VSS – 0.3 V, VDD +0.3 V
DUTGND to GND . . . . . . . . . . . . . .VSS – 0.3 V, VDD +0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . . .150°C
Package Power Dissipation . . . . . . . . . . . . . .(TJ MAX – TA)/θJA
Thermal Impedance θJA
TSSOP (RU-16) . . . . . . . . . . . . . . . . . . . . . . . .150.4°C/W
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . .300°C
IR Reflow, Peak Temperature (< 20 sec) . . . . . . . . . . . .235°CStresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the maximum
deviation, in LSBs, from a straight line passing through the end-
points of the DAC transfer function.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity.
Zero-Scale Error
Zero-scale error is a measure of the output error when all 0s are
loaded to the DAC latch.
Full-Scale Error
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s loaded
into the DAC latch, should be 2 VREF – 1 LSB.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It is the
deviation in slope of the DAC transfer characteristic from ideal.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-s and is mea-
sured when the digital input code is changed by 1 LSB at the
major carry transition.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC, but
is measured when the DAC output is not updated. It is specified
in nV-s and is measured with a full-scale code change on the data
bus, i.e., from all 0s to all 1s and vice versa.
PIN FUNCTION DESCRIPTIONS
AD5530/AD5531–Typical Performance Characteristics
TPC 1.AD5530 Typical INL Plot
TPC 2.AD5530 Typical DNL Plot
TPC 3.AD5531 Typical INL Plot
TPC 4.AD5531 Typical DNL Plot
TPC 5.AD5531 Typical INL Error vs. Temperature
TPC 6.AD5531 Typical DNL Error vs. Temperature

Partno	Mfg	Dc	Qty	Available	Descript
AD5531BRU	AD	N/a	4	avai	Serial Input, ±10 V Output Voltage Range, 14-Bit DAC