AD5450YUJ-REEL7 ,8-Bit High Bandwidth Multiplying DACs with Serial Interfacespecifications T to T unless otherwise noted. DC performance measured withDD REF OUT MIN MAXOP1177, ..
AD5452YRM ,8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interfacespecifications T to T unless otherwise noted. DC performance measured withDD REF OUT MIN MAXOP1177, ..
AD546J ,1 pA Monolithic Electrometer Operational Amplifierapplications requiring both minimallevels of input bias current and low input offset voltage. Appli ..
AD546JN ,1 pA Monolithic Electrometer Operational AmplifierSPECIFICATIONS AD546J AD546KModel Conditions Min Typ Max Min Typ Max Units1INPU ..
AD546KN ,1 pA Monolithic Electrometer Operational Amplifierspecifications are guaranteed, although only those shown in boldface are tested on all production u ..
AD547JH ,High Performance, BiFET Operational AmplifiersSpecifications shown in boldface are tested on all production units at final electrical test. Resu ..
AD9560AKR-REEL ,High Speed Monolithic Pulse Width ModulatorANALOG
DEVICES
AD9560KR ,High Speed Monolithic Pulse Width Modulatorcharacteristics.
Upon close inspection, a similar graphic utilizing pixel-by-pixel
modulation dem ..
AD9561JR ,Pulse Width ModulatorSPECIFICATIONSS SET AD9561JRParameter Temp Min Typ Max UnitsRESOLUTION 8 BitsACCURACY (@ 20 MHz ..
AD9561JR-REEL ,Pulse Width Modulatorfeatures and performance over itspredecessor, the AD9560. An improved ramp topology enablescontrol ..
AD9600ABCPZ-150 , 10-Bit, 105 MSPS/125 MSPS/150 MSPS
AD9601BCPZ-250 , 10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter
AD5450YUJ-REEL7-AD5452YRM
8-Bit High Bandwidth Multiplying DACs with Serial Interface
aREV. PrD Oct, 2003
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
8/10/12/14-Bit High Bandwidth
Multiplying DACs with Serial Interface
PRELIMINARY TECHNICAL DATA*US Patent Number 5,689,257
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
FEATURES
+2.5 V to +5.5 V Supply Operation
50MHz Serial Interface
10MHz Multiplying Bandwidth
±10V Reference Input
8-Lead TSOT & MSOP Packages
Pin Compatible 8, 10, 12 and 14 Bit Current Output DACs
Extended Temperature range –40°C to +125°C
Guaranteed Monotonic
Four Quadrant Multiplication
Power On Reset with brown out detect
<5μμμμμA typical Current Consumption
APPLICATIONS
Portable Battery Powered Applications
Waveform Generators
Analog Processing
Instrumentation Applications
Programmable Amplifiers and Attenuators
Digitally-Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
Gain, offset and Voltage Trimming
GENERAL DESCRIPTIONThe AD5450/AD5451/AD5452/AD5453 are CMOS 8,
10, 12 and 14-bit Current Output digital-to-analog
converters respectively.
These devices operate from a +2.5 V to 5.5 V power sup-
ply, making them suited to battery powered applications
and many other applications.
These DACs utilize double buffered 3-wire serial interface
that is compatible with SPITM, QSPITM, MICROWIRETM
and most DSP interface standards.
On power-up, the internal shift register and latches are
filled with zeros and the DAC output is at zero scale.
As a result of manufacture on a CMOS sub micron
process, they offer excellent four quadrant multiplication
characteristics, with large signal multiplying bandwidths
of 10MHz.
FUNCTIONAL BLOCK DIAGRAMThe applied external reference input voltage (VREF)
determines the full scale output current. An integrated
feedback resistor (RFB) provides temperature tracking and
full scale voltage output when combined with an external
Current to Voltage precision amplifier.
The AD5450/AD5451/AD5452/AD5453 DACs are
available in small 8-lead TSOT & MSOP packages.
AD5450/AD5451/AD5452/AD5453–SPECIFICATIONS1
PRELIMINARY TECHNICAL DATA
(VDD = 2.5 V to 5.5 V, VREF = +10 V, IOUTx = O V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with
OP1177, AC performance with AD9631 unless otherwise noted.)
AD5450/AD5451/AD5452/AD5453
PRELIMINARY TECHNICAL DATA
TIMING CHARACTERISTICS1NOTESSee Figures 1. Temperature range is as follows: Y Version: –40°C to +125°C. Guaranteed by design and characterisation, not subject to
production test. All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
(VREF = +5 V, IOUT2 = O V. All specifications TMIN to TMAX unless otherwise noted.)NOTES
1Temperature range is as follows: Y Version: –40°C to +125°C.
2Guaranteed by design and characterisation, not subject to production test.
Specifications subject to change without notice.
(VDD = 2.5 V to 5.5 V, VREF = +10 V, IOUTx = O V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with
OP1177, AC performance with AD9631 unless otherwise noted.)
AD5450/AD5451/AD5452/AD5453
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS1, 2(TA = +25°C unless otherwise noted)
VDD to GND–0.3 V to +7 V
VREF, RFB to GND–12 V to +12 V
IOUT1 to GND–0.3 V to +7 V
Input Current to any pin except supplies±10 mA
Logic Inputs & Output3-0.3V to VDD +0.3 V
Operating Temperature Range
Industrial (Y Version)–40°C to +125°C
Storage Temperature Range–65°C to +150°C
Junction Temperature+150°C
8 lead MSOP θJA Thermal Impedance206°C/W
8 lead TSOT θJA Thermal Impedance211°C/W
Lead Temperature, Soldering (10seconds)300°C
IR Reflow, Peak Temperature (<20 seconds)+235°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Only one absolute maximum rating may
be applied at any one time. Transient currents of up to 100mA will not cause SCR latchup.Overvoltages at SCLK, SYNC, DIN, will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5450/AD5451/AD5452/AD5453 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTION
PIN CONFIGURATION
MSOP (RM-8)TSOT (UJ-8)
AD5450/AD5451/AD5452/AD5453
PRELIMINARY TECHNICAL DATA
TERMINOLOGY
Relative AccuracyRelative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of full scale reading.
Differential NonlinearityDifferential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adja-
cent codes. A specified differential nonlinearity of -1 LSB max over the operating temperature range ensures monotonic-
ity.
Gain ErrorGain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For
these DACs, ideal maximum output is VREF – 1 LSB. Gain error of the DACs is adjustable to zero with external resis-
tance.
Output Leakage CurrentOutput leakage current is current which flows in the DAC ladder switches when these are turned off. For the IOUT1 termi-
nal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current will flow in the
IOUT2 line when the DAC is loaded with all 1s
Output CapacitanceCapacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling TimeThis is the amount of time it takes for the output to settle to a specified level for a full scale input change. For these de-
vices, it is specifed with a 100 Ω resistor to ground. The settling time specification includes the digital delay from SYNC
rising edge to the full scale output change.
Digital to Analog Glitch lmpulseThe amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current
or voltage signal.
Digital FeedthroughWhen the device is not selected, high frequency logic activity on the device digital inputs may be capacitivelly coupled
through the device to show up as noise on the IOUT pins and subsequently into the following circuitry. This noise is digital
feedthrough.
Multiplying Feedthrough ErrorThis is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all 0s are
loaded to the DAC.
Total Harmonic Distortion (THD)The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental
value is the THD. Usually only the lower order harmonices are included, such as second to fifth.
THD = 20log √(V22 + V32 + V42 + V52)
V1
Digital Intermodulation DistortionSecond order intermodulation (IMD) measurements are the relative magnitudes of the fa and fb tones generated digitally
by the DAC and the second order products at 2fa-fb and 2fb-fa.
Compliance Voltage RangeThe maximum range of (output) terminal voltage for which the device will provide the specified characteristics.
Spurious-Free Dynamic Range(SFDR)It is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate or fs/2). Narrow band SFDR is a measure of SFDR over
an arbitrary window size, in this case 50% of hte fundamental. Digital SFDR is a measure of the usable dymanic range of
the DAC when the signal is a digitally generated sine wave.
PRELIMINARY TECHNICAL DATATPC 1. INL vs. Code (8-Bit DAC)
TPC 4. INL vs. Code (14-Bit DAC)
TPC 7. DNL vs. Code (12-Bit DAC)
TPC 2. INL vs. Code (10-Bit DAC)
TPC 5. DNL vs. Code (8-Bit DAC)
TPC 8. DNL vs. Code (14-Bit DAC)
TPC 3. INL vs. Code (12-Bit DAC)
TPC 6. DNL vs. Code (10-Bit DAC)
TPC 9. INL vs Reference Voltage
AD5450/AD5451/AD5452/AD5453
PRELIMINARY TECHNICAL DATATPC10. DNL vs. Reference Voltage
TPC 13. DNL vs Code - Biased Mode
TPC 16. TUE vs Code
TPC11. Linearity Errors vs. VDD
TPC 14. INL Error vs. Reference -
Biased Mode
TPC 17. Supply Current vs. Clock Freq
TPC12. INL vs Code - Biased Mode
TPC 15. DNL Error vs. Reference -
Biased Mode
TPC 18. Logic Threshold vs Supply
Voltage
