AD5449YRU-REEL7 ,Dual 12-Bit, High Bandwidth Multiplying DACs With Serial Interfaceapplications. Programmable filters and oscillators Composite video The applied external reference i ..
AD544JH ,High Performance, BiFET Operational Amplifiersfeatures offer the user performance superior to existing BiFET4. Low voltage noise (2 μV p-p) and l ..
AD544JH ,High Performance, BiFET Operational AmplifiersFEATURES CONNECTION DIAGRAMUltralow Drift: 1 mV/8C (AD547L)TABLow Offset Voltage: 0.25 mV (AD547L)L ..
AD544KH ,High Performance, BiFET Operational AmplifiersSPECIFICATIONS S A AD542 AD544 AD547Parameter Min Typ M ..
AD544KH ,High Performance, BiFET Operational Amplifiersspecifications are guaranteed after 5 minutes of operation at T = +25°C.A3Input Offset Voltage Drif ..
AD544KH ,High Performance, BiFET Operational Amplifiersspecifications in actual use.0.25 mV on the AD547L, which is achieved by utilizing Analog3. Advance ..
AD9540BCPZ ,655 MHz Low Jitter Clock GeneratorSpecifications.... 4 Modes of Operation ........ 21 Loop Measurement Conditions..... 9 Selectable C ..
AD9549BCPZ , Dual Input Network Clock Generator/Synchronizer
AD9560AKR ,High Speed Monolithic Pulse Width ModulatorFEATURES
Up to 50 MHz Pulse Rate
Autocalibration on Chip
8-Bit Resolution
Center, Leadi ..
AD9560AKR-REEL ,High Speed Monolithic Pulse Width ModulatorANALOG
DEVICES
AD9560KR ,High Speed Monolithic Pulse Width Modulatorcharacteristics.
Upon close inspection, a similar graphic utilizing pixel-by-pixel
modulation dem ..
AD9561JR ,Pulse Width ModulatorSPECIFICATIONSS SET AD9561JRParameter Temp Min Typ Max UnitsRESOLUTION 8 BitsACCURACY (@ 20 MHz ..
AD5449YRU-AD5449YRU-REEL-AD5449YRU-REEL7
Dual 8-Bit, High Bandwidth Multiplying DACs With Serial Interface
Dual 8-,10-,12-Bit High Bandwidth
Multiplying DACs with Serial Interface
Rev. 0
FEATURES
10 MHz multiplying bandwidth
50 MHz serial interface
2.5 V to 5.5 V supply operation
±10 V reference input
Pin compatible 8-, 10-, and 12-bit DACs
Extended temperature range: −40°C to +125°C
16-lead TSSOP package
Guaranteed monotonic
Power-on reset
Daisy-chain mode
Readback function
0.5 µA typical current consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
FUNCTIONAL BLOCK DIAGRAM
VREFB
VREFA
SCLK
SDIN
IOUT1B
IOUT1A
RFBA
IOUT2A
IOUT2B
LDAC04464-0-001
VDD
CLR
RFBB
SDOFigure 1.
GENERAL DESCRIPTION The AD5429/AD5439/AD54491 are CMOS 8-, 10-, and 12-bit
dual-channel current output digital-to-analog converters,
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
These DACs utilize a double-buffered, 3-wire serial interface
that is compatible with SPI®, QSPI™, MICROWIRE™, and most
DSP interface standards. In addition, a serial data out pin (SDO)
allows daisy-chaining when multiple packages are used. Data
readback allows the user to read the contents of the DAC
register via the SDO pin. On power-up, the internal shift
register and latches are filled with zeros and the DAC outputs
are at zero scale.
As a result of manufacture on a CMOS submicron process,
these parts offer excellent 4-quadrant multiplication character-
istics, with large signal multiplying bandwidths of 10 MHz.
The AD5429/AD5439/AD5449 DAC are available in 16-lead
TSSOP packages.
1 US Patent Number 5,689,257.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Characteristics.....................................................................5
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Terminology......................................................................................9
Typical Performance Characteristics...........................................10
General Description.......................................................................15
Unipolar Mode............................................................................15
Bipolar Operation.......................................................................16
Stability........................................................................................16
Single-Supply Applications........................................................17
Positive Output Voltage.............................................................17
Adding Gain................................................................................18
Divider or Programmable Gain Element................................18
Reference Selection....................................................................19
Amplifier Selection....................................................................19
Serial Interface................................................................................20
Microprocessor Interfacing.......................................................22
PCB Layout and Power Supply Decoupling................................24
Power Supplies for the Evaluation Board................................24
Evaluation Board for the DACs................................................24
Overview of AD54xx Devices.......................................................28
Outline Dimensions.......................................................................29
Ordering Guide..........................................................................29
REVISION HISTORY
7/04—Revision 0: Initial Version
SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2A, IOUT2B = 0 V. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured
with OP1177, ac performance with AD9631, unless otherwise noted. Temperature range for Y version is −40°C to +125°C.
Table 1.
Guaranteed by design and characterization, not subject to production test.
TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
See Figure 2 and Figure 3. Temperature range for Y version is −40°C to +125°C. Guaranteed by design and characterization, not subject to
production test. All input signals are specified with tr = tf = ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Table 2. 1 Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register. Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 4.
SCLK
DIN
LDAC1
LDAC2
SYNC
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE
2SYNCHRONOUS LDAC UPDATE MODE
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.04464-0-002
Figure 2. Standalone Mode Timing Diagram
SCLK
SYNC
SDIN
SDO
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain and Readback Modes Timing Diagram
200µAIOL
200µAIOH
TO OUTPUT
PINCL
50pF
VOH (MIN) + VOL (MAX)04464-0-004
Figure 4. Load Circuit for SDO Timing Specifications
ABSOLUTE MAXIMUM RATINGS
Table 3. 1 Overvoltages at SCLK, SYNC, and DIN are clamped by internal diodes.
Current should be limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C unless otherwise noted.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
IOUT2A
RFBA
VREFA
SCLK
LDAC
GND
IOUT1A
IOUT2B
RFBB
VREFB
SYNC
SDINSDO
CLR
VDD
IOUT1B
AD5429/
AD5439/
AD5449
TOP VIEW
(Not to Scale)04464-0-005
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions TERMINOLOGY
Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is typically expressed in
LSBs or as a percentage of full-scale reading.
Differential Nonlinearity Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.
Gain Error Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is VREF − 1 LSB. Gain error of the
DACs is adjustable to zero with external resistance.
Output Leakage Current Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the IOUT1 terminal, it can
be measured by loading all 0s to the DAC and measuring the
IOUT1 current. Minimum current flows in the IOUT2 line when
the DAC is loaded with all 1s.
Output Capacitance Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time The amount of time needed for the output to settle to a
specified level for a full-scale input change. For these devices,
it is specified with a 100 Ω resistor to ground.
Digital-to-Analog Glitch lmpulse The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s,
depending upon whether the glitch is measured as a current
or voltage signal.
Digital Feedthrough When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the
device to show up as noise on the IOUT pins and subsequently
into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal, when all 0s are
loaded to the DAC.
Digital Crosstalk The glitch impulse transferred to the outputs of one DAC in
response to a full-scale code change (all 0s to all 1s and vice
versa) in the input register of the other DAC. It is expressed in
nV-s.
Analog Crosstalk The glitch impulse transferred to the output of one DAC due to
a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa), while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.
Channel-to-Channel Isolation The proportion of input signal from the reference input of one
DAC that appears at the output of the other DAC. It is expressed
in dB.
Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as second to fifth. log20THD=
Intermodulation Distortion The DAC is driven by two combined sine wave references of
frequencies fa and fb. Distortion products are produced at
sum and difference frequencies of mfa ± nfb, where m,
n = 0, 1, 2, 3… Intermodulation terms are those for which m or
n is not equal to zero. The second-order terms include (fa + fb)
and (fa − fb) and the third-order terms are (2fa + fb), (2fa − fb),
(f + 2fa + 2fb) and (fa − 2fb). IMD is defined as fundamentatheofamplituderms
productsdistortiondiffandsumtheofsumIMDlog20=
Compliance Voltage Range The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
TYPICAL PERFORMANCE CHARACTERISTICS
INL (
SB)
0.20CODE
Figure 6. INL vs. Code (8-Bit DAC)
INL (
SB)CODE
Figure 7. INL vs. Code (10-Bit DAC)
INL (
SB)
CODEDNL (LSB)
0.20
CODE
Figure 9. DNL vs. Code (8-Bit DAC)
DNL (LSCODE
Figure 10. DNL vs. Code (10-Bit DAC)
DNL (LS
CODE04462-0-012
INL (LSB)5342789
REFERENCE VOLTAGE04462-0-013
Figure 12. INL vs. Reference Voltage
DNL (LS5342789
REFERENCE VOLTAGE04462-0-014
Figure 13. DNL vs. Reference Voltage
RROR (mV
TEMPERATURE (°C)Figure 14. Gain Error vs. Temperature
INPUT VOLTAGE (V)
CURRE
NT (mA)
4.54.03.53.02.52.01.51.00.5004462-0-022
Figure 15. Supply Current vs. Logic Input Voltage
IOUT
LEAKAGE (nA)
TEMPERATURE (°C)Figure 16. IOUT1 Leakage Current vs. Temperature
CURRE
NT (
TEMPERATURE (°C)Figure 17. Supply Current vs. Temperature
(mA)
10k1k101001100k1M10M100M
FREQUENCY (Hz)Figure 18. Supply Current vs. Update Rate
–181001k10k100k1M10M100M
FREQUENCY (Hz)
GAIN (
–9604462-0-026
10Figure 19. Reference Multiplying Bandwidth vs. Frequency and Code
GAIN (dB)
10k1k101001100k1M10M100M
FREQUENCY (Hz)Figure 20. Reference Multiplying Bandwidth–All 1s Loaded
10k100k1M10M100M
FREQUENCY (Hz)
GAIN (Figure 21. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
OUTPUT VOLTAGE (20406080100120140160180200
TIME (ns)Figure 22. Midscale Transition, VREF = 0 V
OUTPUT VOLTAGE (20406080100120140160180200
TIME (ns)–1.68
Figure 23. Midscale Transition, VREF = 3.5 V
FREQUENCY (Hz)
RR (04462-0-043
10Figure 24. Power Supply Rejection vs. Frequency
THD + N (dB)
1001k11010k100k1M
FREQUENCY (Hz)Figure 25. THD + Noise vs. Frequency
DR (dB)20406080100120140160180200
fOUT (kHz)Figure 26. Wideband SFDR vs. fOUT Frequency
DR (dB)1002003004005006007008009001000
fOUT (kHz)Figure 27. Wideband SFDR vs. fOUT Frequency
SFDR (dB)
FREQUENCY (MHz)
–20681012
Figure 28. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
SFDR (dB)
FREQUENCY (MHz)
–90
Figure 29. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
SFDR (dB)
FREQUENCY (MHz)
0.51.53.03.54.01.02.02.54.55.0
Figure 30. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
04462-0-050
FREQUENCY (MHz)
SFDR (dB)
450500550600Figure 31. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
DR (dB)150
FREQUENCY (MHz)7080130140
–100100110120
Figure 32. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
04462-0-052
FREQUENCY (MHz)
(dB)120758085115
–90100105110Figure 33. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
(dB)–50
FREQUENCY (kHz)300350100150200250
Figure 34. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
1001k10k100k
FREQUENCY (Hz)OUTP
UT NOIS
(nV
Figure 35. Output Noise Spectral Density
GENERAL DESCRIPTION The AD5429/AD5439/AD5449 are 8-, 10-, and 12-bit dual-
channel current output DACs consisting of a standard inverting
R−2R ladder configuration. A simplified diagram of one DAC
channel for the AD5449 is shown in Figure 36. The feedback
resistor RFB has a value of R. The value of R is typically 10 kΩ
(minimum 8 kΩ and maximum 12 kΩ). If IOUT1 and IOUT2 are
kept at the same potential, a constant current flows in each
ladder leg, regardless of digital input code. Therefore, the input
resistance presented at VREF is always constant.
RFBA
IOUT1A
IOUT2A
VREFA04464-0-006
Figure 36. Simplified Ladder
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of
the DACs, making the devices extremely versatile and allowing
them to be configured in several operating modes, such as
unipolar mode, bipolar output mode, or single-supply mode.
UNIPOLAR MODE Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 37.
When an output amplifier is connected in unipolar mode, the
output voltage is given by
REFOUTDVV2/×−=
where D is the fractional representation of the digital word
loaded to the DAC, and n is the number of bits. = 0 to 255 (AD5429) = 0 to 1023 (AD5439) = 0 to 4095 (AD5449)
With a fixed 10 V reference, the circuit shown in Figure 37 gives
a unipolar 0 V to −10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 5 shows the relationship between digital code and the
expected output voltage for unipolar operation for the AD5429.
Table 5. Unipolar Code Table NOTES:
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
3. DAC B OMITTED FOR CLARITY.
VDD–VREF
AGND
VREF
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 37. Unipolar Operation
BIPOLAR OPERATION In some applications, it might be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and three external resistors, as shown in Figure 38.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication. When connected in bipolar mode, the output
voltage is REFnREFOUTVDV−×=−12/
where D is the fractional representation of the digital word
loaded to the DAC, and n is the number of bits. = 0 to 255 (AD5429) = 0 to 1023 (AD5439) = 0 to 4095 (AD5449)
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation with the AD5429.
Table 6. Bipolar Code Table
STABILITY In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as closely as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking can occur, if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open loop
response, which can cause ringing or instability in the closed-
loop applications circuit.
As shown in Figure 37 and Figure 38, an optional compensation
capacitor, C1, can be added in parallel with RFB for stability. Too
small a value of C1 can produce ringing at the output, while too
large a value can adversely affect the settling time. C1 should be
found empirically, but 1 pF to 2 pF is generally adequate for the
compensation.
04464-0-008
TO +VREF
VREF±10V
NOTES:
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
4. DAC B AND ADDITIONAL PINS OMITTED FOR CLARITY.
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
R3 AND R4.
20kΩ
AGNDFigure 38. Bipolar Operation
