AD5432YRM-AD5443YRM Fast Delivery |IC PHOENIX CO.,LIMITED

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AD5432YRM-AD5443YRM
High Bandwidth CMOS 8-Bit Serial Interface Multiplying D/A Converter
REV.0
8-/10-/12-Bit High Bandwidth
Multiplying DACs with Serial Interface
FEATURES
3.0 V to 5.5 V Supply Operation
50 MHz Serial Interface
10 MHz Multiplying Bandwidth
�10 V Reference Input
Low Glitch Energy < 2 nV-s
Extended Temperature Range –40�C to +125�C
10-Lead MSOP Package
Pin Compatible 8-, 10-, and 12-Bit Current
Output DACs
Guaranteed Monotonic
4-Quadrant Multiplication
Power-On Reset with Brownout Detection
Daisy-chain Mode
Readback Function
0.4 �A Typical Power Consumption
APPLICATIONS
Portable Battery-Powered Applications
Waveform Generators
Analog Processing
Instrumentation Applications
Programmable Amplifiers and Attenuators
Digitally Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
Gain, Offset, and Voltage Trimming
GENERAL DESCRIPTION
The AD5426/AD5432/AD5443 are CMOS 8-, 10-, and 12-bit
current output digital-to-analog converters, respectively.
These devices operate from a 3.0 V to 5.5 V power supply,
making them suited to battery-powered applications and many
other applications.
These DACs utilize double buffered 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most
DSP interface standards. In addition, a serial data out pin (SDO)
allows for daisy-chaining when multiple packages are used. Data
readback allows the user to read the contents of the DAC register
via the SDO pin. On power-up, the internal shift register and
latches are filled with 0s and the DAC outputs are at zero scale.
As a result of manufacture on a CMOS submicron process, they
offer excellent 4-quadrant multiplication characteristics, with
large signal multiplying bandwidths of 10 MHz.
FUNCTIONAL BLOCK DIAGRAM
*U.S. Patent No. 5,689,257
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor (RFB)
provides temperature tracking and full-scale voltage output when
combined with an external current to voltage precision amplifier.
The AD5426/AD5432/AD5443 DACs are available in small
10-lead MSOP packages.
AD5426/AD5432/AD5443–SPECIFICATIONS1
(VDD = 3 V to 5.5 V, VREF = 10 V, IOUTx = O V. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177, AC
performance with AD8038, unless otherwise noted.)
DIGITAL INPUTS/OUTPUT
DYNAMIC PERFORMANCE
AD5426/AD5432/AD5443
POWER REQUIREMENTS
NOTESTemperature range is as follows: Y version: –40°C to +125°C.Guaranteed by design and characterization, not subject to production test.
Specifications subject to change without notice.
AD5426/AD5432/AD5443
TIMING CHARACTERISTICS1
NOTES
1See Figures 1 and 2. Temperature range is as follows: Y version: –40°C to +125°C. Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2Falling or rising edge as determined by control bits of serial word.
3Daisy-chain and readback modes cannot operate at max clock frequency. SDO timing specifications measured with load circuit as shown in Figure 3.
Specifications subject to change without notice.
(VDD = 3 V to 5.5 V, VREF = 10 V, IOUT2 = O V. All specifications TMIN to TMAX, unless otherwise noted.)
Figure 1.Standalone Mode Timing Diagram
Figure 2. Daisy-chain and Readback Modes Timing Diagram
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VREF, RFB to GND . . . . . . . . . . . . . . . . . . . . . .–12 V to +12 V
IOUT1, IOUT2 to GND . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Logic Inputs and Output3 . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Extended Industrial (Y Version) . . . . . . . .–40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
10-lead MSOP θJA Thermal Impedance . . . . . . . . . . .206°C/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . .300°C
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . .235°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2 Transient currents of up to 100 mA will not cause SCR latchup.Overvoltages at SCLK, SYNC, and DIN, will be clamped by internal diodes.
Figure 3.Load Circuit for SDO Timing Specifications
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5426/AD5432/AD5443 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
AD5426/AD5432/AD5443
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
TPC 1.INL vs. Code (8-Bit DAC)
TPC 4.DNL vs. Code (8-Bit DAC)
TPC 7.INL vs. Reference Voltage
TPC 2.INL vs. Code (10-Bit DAC)
TPC 5. DNL vs. Code (10-Bit DAC)
TPC 8.DNL vs. Reference Voltage
TPC 3.INL vs. Code (12-Bit DAC)
TPC 6.DNL vs. Code (12-Bit DAC)
TEMPERATURE (�C)
ERROR (mV)
–60–40–20020406080100120140
TPC 9.Gain Error vs. Temperature
AD5426/AD5432/AD5443
TPC 10.Linearity vs. VBIAS
Voltage Applied to IOUT2

TPC 13.Gain and Offset Errors
vs. VBIAS Voltage Applied to IOUT2
TPC 16. Supply Current vs.
Logic Input Voltage, SYNC
(SCLK, DATA = 0)

TPC 11.Linearity vs. VBIAS
Voltage Applied to IOUT2

TPC 14.Linearity vs. VBIAS
Voltage Applied to IOUT2
TPC 17.IOUT1 Leakage Current
vs. Temperature
TPC 12.Gain and Offset Errors vs.
VBIAS Voltage Applied to IOUT2
TPC 15.Linearity vs. VBIAS
Voltage Applied to IOUT2
CURRENT (
TEMPERATURE (�C)
120–40
TPC 18.Supply Current vs.
Temperature
TPC 19.Supply Current vs.
Update Rate
TPC 22.Reference Multiplying
Bandwidth vs. Frequency and
Compensation Capacitor
TPC 25.Power Supply Rejection vs.
Frequency

TPC 20.Reference Multiplying
Bandwidth vs. Frequency and Code
TPC 23.Midscale Transition
VREF = 0 V
TPC 26.THD and Noise vs.
Frequency
TPC 21.Reference Multiplying
Bandwidth—All Ones Loaded
TPC 24.Midscale Transition
VREF = 3.5 V
TPC 27. Supply Current
vs. Temperature
AD5426/AD5432/AD5443

TPC 28. Threshold Voltages
vs. Supply Voltage
TPC 31. Wideband SFDR
fOUT = 50 kHz, Update = 1 MHz
TPC 34. Narrowband (±50%)
SFDR fOUT = 20 kHz,
Update = 1 MHz
TPC 29. Wideband SFDR vs.
fOUT Frequency (AD5443)
TPC 32. Wideband SFDR
fOUT = 20 kHz, Update = 1 MHz
FREQUENCY (Hz)1520253530
–90
TPC 35. Narrowband (±50%)
IMD, fOUT = 20 kHz, 25 kHz,
Update = 1 MHz
TPC 30. Wideband SFDR vs.
fOUT Frequency (AD5426)
TPC 33. Narrowband (±50%)
SFDR fOUT = 50 kHz,
Update = 1 MHz
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for 0 and full scale and is normally expressed in LSBs
or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of –1 LSB max over
the operating temperature range ensures monotonicity.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is VREF – 1 LSB. Gain error of
the DACs is adjustable to 0 with external resistance.
Output Leakage Current
Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the IOUT1 terminal, it
can be measured by loading all 0s to the DAC and measuring
the IOUT1 current. Minimum current will flow in the IOUT2 line
when the DAC is loaded with all 1s.
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full scale input change. For these devices, it
is specified with a 100 Ω resistor to ground.
The settling time specification includes the digital delay from
SYNC rising edge to the full-scale output charge.
Digital to Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device digital inputs may be capacitively coupled through the
device to show up as noise on the IOUT pins and subsequently
into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal, when all 0s are
loaded to the DAC.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms
sum of the harmonics of the DAC output to the fundamental
value is the THD. Usually only the lower order harmonics are
included, such as second to fifth.
Digital Intermodulation Distortion
Second-order intermodulation distortion (IMD) measurements
are the relative magnitude of the fa and fb tones generated digi-
tally by the DAC and the second-order products at 2fa – fb and
2fb – fa.
Spurious-Free Dynamic Range (SFDR)
It is the usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the mea-
sure of difference in amplitude between the fundamental and
the largest harmonically or nonharmonically related spur from
dc to full Nyquist bandwidth (half the DAC sampling rate, or
fS/2). Narrow band SFDR is a measure of SFDR over an arbi-
trary window size, in this case 50% of the fundamental. Digital
SFDR is a measure of the usable dynamic range of the DAC
when the signal is digitally generated sine wave.
AD5426/AD5432/AD5443
DAC SECTION
The AD5426, AD5432, and AD5443 are 8-, 10-, and 12-bit cur-
rent output DACs consisting of a standard inverting R-2R ladder
configuration. A simplified diagram for the 8-bit AD54246 is
shown in Figure 4. The feedback resistor RFB has a value of R.
The value of R is typically 10 kΩ (minimum 8 kΩ and maximum
12 kΩ). If IOUT1 and IOUT2 are kept at the same potential, a con-
stant current flows in each ladder leg, regardless of digital input
code. Therefore, the input resistance presented at VREF is always
constant and nominally of value R. The DAC output (IOUT) is
code-dependent, producing various resistances and capacitances.
External amplifier choice should take into account the variation
in impedance generated by the DAC on the amplifiers inverting
input node.
Figure 4.Simplified Ladder
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals
of the DAC, making the device extremely versatile and allowing
it to be configured in several different operating modes, for
example, to provide a unipolar output, 4-quadrant multiplica-
tion in bipolar mode, or in single-supply modes of operation.
Note that a matching switch is used in series with the internal
RFB feedback resistor. If users attempt to measure RFB, power
must be applied to VDD to achieve continuity.
SERIAL INTERFACE
The AD5426/AD5432/AD5443 have an easy to use 3-wire inter-
face that is compatible with SPI/QSPI/MICROWIRE and DSP
interface standards. Data is written to the device in 16 bit words.
This 16-bit word consists of 4 control bits and either 8, 10, or
12 data bits as shown in Figure 5. The AD5443 uses all 12 bits of
DAC data. The AD5432 uses 10 bits and ignores the 2 LSBs,
while the AD5426 uses 8 bits and ignores the last 4 bits.
Low Power Serial Interface
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, i.e., on
the falling edge of SYNC. The SCLK and DIN input buffers are
powered down on the rising edge of SYNC.
DAC Control Bits C3 to C0
Control Bits C3 to C0 allow control of various functions of the
DAC as seen in Table I. Default settings of the DAC on power
on are as follows:
Data clocked into shift register on falling clock edges; daisy-chain
mode is enabled. Device powers on with zero-scale load to the
DAC register and IOUT lines.
The DAC control bits allow the user to adjust certain features
on power-on, for example, daisy-chaining may be disabled if not
in use, active clock edge may be changed to rising edge, and DAC
output may be cleared to either zero or midscale. The user may
also initiate a readback of the DAC register contents for verifi-
cation purposes.
Table I.DAC Control Bits
Figure 5a. AD5426 8-Bit Input Shift Register Contents
Figure 5b. AD5432 10-Bit Input Shift Register Contents

Partno	Mfg	Dc	Qty	Available	Descript
AD5432YRM	AD	N/a	1	avai	High Bandwidth CMOS 10-Bit Serial Interface Multiplying D/A Converter
AD5443YRM	AD	N/a	25	avai	High Bandwidth CMOS 12-Bit Serial Interface Multiplying D/A Converter