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AD5415YRU
Dual 12-Bit, High Bandwidth, Multiplying DAC with 4 Quadrant Resistors and Serial Interface
Dual 12-Bit, High Bandwidth, Multiplying DAC
with 4-Quadrant Resistors and Serial Interface
Rev. 0
FEATURES
On-chip 4-quadrant resistors allow flexible output ranges
10 MHz multiplying bandwidth
50 MHz serial interface
2.5 V to 5.5 V supply operation
±10 V reference input
Extended temperature range: −40°C to +125°C
24-lead TSSOP package
Guaranteed monotonic
Power-on reset
Daisy-chain mode
Readback function
0.5 µA typical current consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
GENERAL DESCRIPTION The AD54151 is a CMOS 12-bit, dual-channel, current output
digital-to-analog converter. This device operates from a 2.5 V to
5.5 V power supply, making it suited to battery-powered appli-
cations as well as many other applications.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier. In addition, this device contains all the
4-quadrant resistors necessary for bipolar operation and other
configuration modes.
This DAC utilizes a double-buffered 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP
interface standards. In addition, a serial data out pin (SDO)
allows for daisy-chaining when multiple packages are used.
Data readback allows the user to read the contents of the DAC
register via the SDO pin. On power-up, the internal shift
register and latches are filled with zeros, and the DAC outputs
are at zero scale. As a result of manufacture on a CMOS submi-
cron process, this part offers excellent 4-quadrant multiplication
characteristics, with large-signal multiplying bandwidths of
10 MHz.
1US Patent Number 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
VDD
SCLK
SDIN
GND
SDO
SYNC
LDAC
R3AR2_3AR2AVREFAR1A
R3BR2_3BR2BVREFBR1B
RFBA
IOUT1A
IOUT2A
IOUT1B
IOUT2B
RFBB
CLR04461-0-001
Figure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Characteristics................................................................5
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Terminology......................................................................................9
Typical Performance Characteristics...........................................10
General Description.......................................................................15
DAC Section................................................................................15
Unipolar Mode............................................................................15
Bipolar Operation.......................................................................16
Stability........................................................................................16
Single-Supply Applications............................................................17
Voltage Switching Mode of Operation....................................17
Positive Output Voltage.............................................................17
Adding Gain................................................................................17
Divider or Programmable Gain Element................................17
Reference Selection....................................................................18
Amplifier Selection....................................................................18
Serial Interface................................................................................20
Low Power Serial Interface.......................................................20
Control Register.........................................................................20
SYNC Function...........................................................................21
Daisy-Chain Mode.....................................................................21
Standalone Mode........................................................................21
LDAC Function..........................................................................21
Microprocessor Interfacing.......................................................22
PCB Layout and Power Supply Decoupling................................24
Evaluation Board for the DAC.................................................24
Power Supplies for the Evaluation Board................................24
Outline Dimensions.......................................................................28
Ordering Guide..........................................................................28
REVISION HISTORY
7/04—Revision 0: Initial Version SPECIFICATIONS Temperature range for Y Version: −40°C to +125°C.
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2A, IOUT2B = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
DC performance measured with OP1177, ac performance with AD8038, unless otherwise noted.
Table 1. Guaranteed by design and characterization, not subject to production test.
TIMING CHARACTERISTICS Temperature range for Y Version: −40°C to +125°C. See Figure 2 and Figure 3.
Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2. Falling or rising edge as determined by the control bits of serial word. Strong or weak SDO driver selected via the control register.
2 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with a load circuit, as shown in . Figure 4
SCLK
DIN
LDAC1
LDAC2
SYNC
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE
2SYNCHRONOUS LDAC UPDATE MODE
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.04461-0-002
Figure 2. Standalone Mode Timing Diagram
SCLK
SYNC
SDIN
SDO
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain and Readback Modes Timing Diagram
200µAIOL
200µAIOH
TO OUTPUT
PINCL
50pF
VOH (MIN) + VOL (MAX)04461-0-004
Figure 4. Load Circuit for SDO Timing Specifications
ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Table 3. 1 Overvoltages at SCLK, SYNC, and DIN are clamped by internal diodes.
Current should be limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SDIN
SCLK
GND
VREFA
IOUT1A
IOUT2A
RFBA
R1A
R3A
R2_3A
R2A
LDAC04461-0-005
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
TERMINOLOGY
Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero scale and full scale, and is normally expressed
in LSB or as a percentage of full-scale reading.
Differential Nonlinearity Differential nonlinearity is the difference in the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.
Gain Error Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is VREF − 1 LSB. Gain error of the
DACs is adjustable to zero with external resistance.
Output Leakage Current Output leakage current is current that flows in the DAC ladder
switches when they are turned off. For the IOUT1 terminal, it can
be measured by loading all 0s to the DAC and measuring the
IOUT1 current. Minimum current flows in the IOUT2 line when
the DAC is loaded with all 1s.
Output Capacitance Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time The amount of time it takes for the output to settle to a speci-
fied level for a full-scale input change. For these devices, it is
specified with a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s depend-
ing upon whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough When the device is not selected, high frequency logic activity on
the device’s digital inputs is capacitively coupled through the
device to show up as noise on the IOUT pins and subsequently
into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Digital Crosstalk The glitch impulse transferred to the outputs of one DAC in
response to a full-scale code change (all 0s to all 1s and vice
versa) in the input register of the other DAC. It is expressed
in nV-s.
Analog Crosstalk The glitch impulse transferred to the output of one DAC due to
a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa), while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.
Channel-to-Channel Isolation The proportion of input signal from one DAC reference input
that appears at the output of the other DAC and is expressed
in dB.
Harmonic Distortion The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the total harmonic distortion (THD). Usually only the lower-
order harmonics are included, such as second to fifth. log20THD=
Intermodulation Distortion The DAC is driven by two combined sine wave references of
frequencies fa and fb. Distortion products are produced at sum
and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3 ...
Intermodulation terms are those for which m or n is not equal
to zero. The second-order terms include (fa + fb) and (fa − fb)
and the third-order terms are (2fa + fb), (2fa − fb), (f + 2fa +
2fb) and (fa − 2fb). IMD is defined as fundamentatheofamplituderms
productsdistortiondiffandsumtheofsumIMDlog20=
Compliance Voltage Range The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
TYPICAL PERFORMANCE CHARACTERISTICS
INL (
SB)
CODEFigure 6. INL vs. Code (12-Bit DAC)
DNL (LS
CODEFigure 7. DNL vs. Code (12-Bit DAC)
INL (
SB)534278
REFERENCE VOLTAGE04461-0-008
10
DNL (LS534278
REFERENCE VOLTAGE04461-0-009
10Figure 9. DNL vs. Reference Voltage
RROR (mV
TEMPERATURE (°C)Figure 10. Gain Error vs. Temperature
INPUT VOLTAGE (V)
CURRE
NT (mA)
4.54.03.53.02.52.01.51.00.5004461-0-011
OUT
LE
AKAGE
(nA)
TEMPERATURE (°C)Figure 12. Iout1 Leakage Current vs. Temperature
CURRE
NT (
TEMPERATURE (°C)Figure 13. Supply Current vs. Temperature
IDD
(mA)
10k1k101001100k1M10M100M
FREQUENCY (Hz)Figure 14. Supply Current vs. Update Rate
–181001k10k100k1M10M100M
FREQUENCY (Hz)
–9604461-0-015
10Figure 15. Reference Multiplying Bandwidth vs. Frequency and Code
GAIN (
10k1k101001100k1M10M100M
FREQUENCY (Hz)Figure 16. Reference Multiplying Bandwidth–All Ones Loaded
10k100k1M10M100M
FREQUENCY (Hz)Figure 17. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
OUTPUT VOLTAGE (V)20406080100120140160180200
TIME (ns)Figure 18. Midscale Transition, VREF = 0 V
OUTPUT VOLTAGE (V)20406080100120140160180200
TIME (ns)–1.69
Figure 19. Midscale Transition, VREF = 3.5 V
–601001k10k100k1M10M
FREQUENCY (Hz)
PSRR (d04461-0-020
10Figure 20. Power Supply Rejection vs. Frequency
THD + N (dB)
1001k11010k100k1M
FREQUENCY (Hz)Figure 21. THD and Noise vs. Frequency
DR (dB)20406080100120140160180200
fOUT (kHz)Figure 22. Wideband SFDR vs. fOUT Frequency
DR (dB)1002003004005006007008009001000
fOUT (kHz)Figure 23. Wideband SFDR vs. fOUT Frequency
FREQUENCY (MHz)
–20681012
Figure 24. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
FREQUENCY (MHz)
–90
Figure 25. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
DR (
FREQUENCY (MHz)
0.51.53.03.54.01.02.02.54.55.0
Figure 26. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
04461-0-027
FREQUENCY (MHz)
DR (
450500550600Figure 27. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
(d150
FREQUENCY (MHz)7080130140
–100100110120
Figure 28. Narrow-Band SFDR, fOUT = 100 kHz, MCLK = 25 MHz
04461-0-029
FREQUENCY (MHz)
–90100105110Figure 29. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
(dB)–50
FREQUENCY (kHz)300350100150200250
Figure 30. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
1001k10k100k
FREQUENCY (Hz) (n
Figure 31. Output Noise Spectral Density
