AD5405YCP Fast Delivery |IC PHOENIX CO.,LIMITED

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AD5405YCP
Dual 12-Bit , High Bandwidth, Multiplying DAC with 4 Quadrant Resistors and Parallel Interface
Dual 12-Bit, High Bandwidth, Multiplying DAC with
4-Quadrant Resistors and Parallel Interface
Rev. 0

FEATURES
On chip 4-quadrant resistors allow flexible output ranges
10 MHz multiplying bandwidth
Fast parallel interface write cycle: 58 MSPS
2.5 V to 5.5 V supply operation
±10 V reference input
Extended temperature range: −40°C to 125°C
40-lead LFCSP package
Guaranteed monotonic
4-quadrant multiplication
Power-on reset
Readback function
.5 µA typical current consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally-controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
GENERAL DESCRIPTION
The AD54051 is a dual CMOS, 12-bit, current output digital-
to-analog converter (DAC).This device operates from a 2.5 V to
5.5 V power supply, making it suited to battery-powered and
other applications.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external I-to-V precision
amplifier. This device also contains all the 4-quadrant resistors
necessary for bipolar operation and other configuration modes.
This DAC utilizes data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with zeros and the DAC
outputs are at zero scale.
As a result of manufacture with a CMOS submicron process, the
device offers excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The AD5405 has a 6 mm × 6 mm, 40-lead LFCSP package. US Patent Number 5,689,257.
VREFA
VREFB
VDD
DB0
DB11
DATA
INPUTS
DAC A/B
R/W
GNDIOUT1B
IOUT1A
RFBA
R1A
R3AR2AR2_3A
R3BR2BR2_3B
R1B
IOUT2A
IOUT2BLDAC
RFB B
Figure 1. AD5405 Functional Block Diagram
TABLE OF CONTENTS
Specifications.....................................................................................3
Timing Characteristics.....................................................................5
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Descriptions.............................7
Typical Performance Characteristics.............................................8
Terminology....................................................................................13
General Description.......................................................................14
DAC Section................................................................................14
Circuit Operation.......................................................................14
Single-Supply Applications........................................................15
Positive Output Voltage.............................................................15
Adding Gain................................................................................15
Used as a Divider or Programmable Gain Element...............16
Reference Selection....................................................................16
Amplifier Selection....................................................................16
Parallel Interface.........................................................................17
Microprocessor Interfacing.......................................................17
PCB Layout and Power Supply Decoupling...........................17
Evaluation Board for the DACs................................................18
Overview of AD54xx Devices.......................................................22
Outline Dimensions.......................................................................23
Ordering Guide..........................................................................23
REVISION HISTORY
7/04—Revision 0: Initial Version
SPECIFICATIONS1
VDD = 2.5 V to 5.5 V, VREFA = VREFB = 10 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured
with OP1177, AC performance with AD9631, unless otherwise noted.
Table 1.
Output Noise Spectral Density 25 nV/√Hz @ 1 kHz
Temperature range for Y version is −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
See Temperature range for Y version is −40°C to +125°C. Guaranteed by design and characterization, not subject to production test. Figure 2.
2 All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Digital output timing measured
with load circuit in . Figure 3
R/W
DATA
DACA/DACB
04463-0-002
Figure 2. Timing Diagram
IOL200µA
IOH200µA
OUTPUT
PIN
VOH (MIN)+ VOL (MAX)
04463-0-003
Figure 3. Load Circuit for Data Timing Specifications
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.

1 Over voltages at DBx, LDAC, CS, and W/R are clamped by internal diodes.
Current should be limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1INDICATOR
AD5405
TOP VIEWR1AR2AR2_3AR3AVREFADGNDLDACDAC A/BNCDB11
NC=NOCONNECT
10 11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
30 R1B
29 R2B
28 R2_3B
27 R3B
26VREFB
25VDD
24 CLR
23 R/W
22 CS
21 DB0
40 R
39 I
OUT
38 I
OUT
37 N
36 N
35 N
34 N
33 I
OUT
32 I
OUT
31 R
04463-0-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
TYPICAL PERFORMANCE CHARACTERISTICS
INL (
SB)
CODE
Figure 5. INL vs. Code (12-Bit DAC)
DNL (LS
CODE
Figure 6. DNL vs. Code (12-Bit DAC)
INL (
SB)534278910
REFERENCE VOLTAGE
DNL (LS5342789
REFERENCE VOLTAGE
04463-0-034
Figure 8. DNL vs. Reference Voltage
RROR (mV
TEMPERATURE (°C)
Figure 9. Gain Error vs. Temperature
INPUT VOLTAGE (V)
CURRE
NT (mA)
4.54.03.53.02.52.01.51.00.50
04463-0-013
IOUT
LE
AKAGE
(nA)
TEMPERATURE (°C)
Figure 11. IOUT1 Leakage Current vs. Temperature
CURRE
NT (
TEMPERATURE (°C)
Figure 12. Supply Current vs. Temperature
IDD
(mA)
10k1k101001100k1m10m100m
FREQUENCY (Hz)
Figure 13. Supply Current vs. Update Rate
–181001k10k100k1M10M100M
FREQUENCY (Hz)
GAIN (
–96
04463-0-01410
Figure 14. Reference Multiplying Bandwidth vs. Frequency and Code
GAIN (
10k1k101001100k1m10m100m
FREQUENCY (Hz)
Figure 15. Reference Multiplying Bandwidth–All 1s Loaded
10k100k1M10M100M
FREQUENCY (Hz)
GAIN (
Figure 16. Reference Multiplying Bandwidth vs. Frequency and Compensation
OUTPUT VOLTAGE (V)20406080100120140160180200
TIME (ns)
Figure 17. Midscale Transition, VREF = 0 V
OUTPUT VOLTAGE (V)20406080100120140160180200
TIME (ns)
–1.68
Figure 18. Midscale Transition, VREF = 3.5 V
FREQUENCY (Hz)
PSRR (d
04463-0-02610
Figure 19. Power Supply Rejection vs. Frequency
THD + N (dB)
1001k11010k100k1M
FREQUENCY (Hz)
Figure 20. THD and Noise vs. Frequency
DR (dB)20406080100120140160180200
fOUT (kHz)
Figure 21. Wideband SFDR vs. fOUT Frequency
DR (dB)1002003004005006007008009001000
fOUT (kHz)
Figure 22. Wideband SFDR vs. fOUT Frequency
DR (dB)
FREQUENCY (MHz)
–204681012
Figure 23. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
DR (dB)
FREQUENCY (MHz)
–90
Figure 24. Wideband SFDR, fOUT =500 kHz, Clock = 10 MHz
DR (dB)
FREQUENCY (MHz)
0.51.53.03.54.01.02.02.54.55.0
Figure 25. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
04463-0-021FREQUENCY (MHz)
DR (dB)
450500550600
Figure 26. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
DR (dB)150
FREQUENCY (MHz)7080130140
–100100110120
Figure 27. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
04463-0-023FREQUENCY (MHz)
(dB)120758085115
–90100105110
Figure 28. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
(dB)–50
FREQUENCY (kHz)300350100150200250
Figure 29. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
1001k10k100k
FREQUENCY (Hz)
OUTP
UT NOIS
(nV
Figure 30. Output Noise Spectral Density

Partno	Mfg	Dc	Qty	Available	Descript
AD5405YCP	AD	N/a	55	avai	Dual 12-Bit , High Bandwidth, Multiplying DAC with 4 Quadrant Resistors and Parallel Interface