AD538BD ,Real-Time Analog Computational Unit ACUCHARACTERISTICSOffset Voltage V = 0, V = –600 mV – 200 6500 – 100 6250 – 200 6500 m VY CT = T to T ..
AD538BD ,Real-Time Analog Computational Unit ACUFEATURESm
AD538AD-AD538BD
Real-Time Analog Computational Unit ACU
REV.C
Real-Time Analog
Computational Unit (ACU)
FUNCTIONAL BLOCK DIAGRAM
+10V
–VS
+VS
+2V
PWR
GND
SIGNAL
GND
FEATURES
VOUT = VY
Wide Dynamic Range (Denominator) –1000:1
Simultaneous Multiplication and Division
Resistor-Programmable Powers and Roots
No External Trims Required
Low Input Offsets <100 mV
Low Error 60.25% of Reading (100:1 Range)
+2 V and +10 V On-Chip References
Monolithic Construction
APPLICATIONS
One- or Two-Quadrant Mult/Div
Log Ratio Computation
Squaring/Square Rooting
Trigonometric Function Approximations
Linearization Via Curve Fitting
Precision AGC
Power Functions
PRODUCT DESCRIPTIONThe AD538 is a monolithic real-time computational circuit that
provides precision analog multiplication, division and exponen-
tiation. The combination of low input and output offset voltages
and excellent linearity results in accurate computation over an
unusually wide input dynamic range. Laser wafer trimming makes
multiplication and division with errors as low as 0.25% of read-
ing possible, while typical output offsets of 100mV or less add to
the overall off-the-shelf performance level. Real-time analog
signal processing is further enhanced by the device’s 400 kHz
bandwidth.
The AD538’s overall transfer function is VO = VY (VZ/VX)m.
Programming a particular function is via pin strapping. No
external components are required for one-quadrant (positive
input) multiplication and division. Two-quadrant (bipolar
numerator) division is possible with the use of external level
shifting and scaling resistors. The desired scale factor for both
multiplication and division can be set using the on-chip +2V or
+10V references, or controlled externally to provide simulta-
neous multiplication and division. Exponentiation with an m
value from 0.2 to 5 can be implemented with the addition of
one or two external resistors.
Direct log ratio computation is possible by using only the log
ratio and output sections of the chip. Access to the multiple
summing junctions adds further to the AD538’s flexibility.
Finally, a wide power supply range of –4.5 V to –18 V allows
operation from standard –5 V, –12 V and –15 V supplies.
The AD538 is available in two accuracy grades (A and B) over
the industrial (–25°C to +85°C) temperature range and one
grade (S) over the military (–55°C to +125°C) temperature
range. The device is packaged in an 18-lead TO-118 hermetic
side-brazed ceramic DIP. A-grade chips are also available.
PRODUCT HIGHLIGHTSReal-time analog multiplication, division and exponentiation.High accuracy analog division with a wide input dynamic
range.On-chip +2 V or +10 V scaling reference voltages.Both voltage and current (summing) input modes.Monolithic construction with lower cost and higher reliability
than hybrid and modular circuits.
AD538–SPECIFICATIONSFREQUENCY RESPONSE
TEMPERATURE RANGE
PACKAGE OPTIONS
NOTESOver the 100 mV to 10 V operating range total error is the sum of a percent of reading term and an output offset. With this input dynamic range the input offset
contribution to total error is negligible compared to the percent of reading error. Thus, it is specified indirectly as a part of the percent of reading error.The most accurate representation of total error with low level inputs is the summation of a percent of reading term, an output offset and an input offset multiplied by
the incremental gain (VY + VZ) VX.When using supplies below –13 V, the 10 V reference pin must be connected to the 2 V pin in order for the AD538 to operate correctly.
(VS = 615 V, TA = +258C unless otherwise noted)
RE-EXAMINATION OF MULTIPLIER/DIVIDER
ACCURACYTraditionally, the “accuracy” (actually the errors) of analog
multipliers and dividers have been specified in terms of percent
of full scale. Thus specified, a 1% multiplier error with a 10 V
full-scale output would mean a worst case error of +100 mV at
“any” level within its designated output range. While this type
of error specification is easy to test evaluate, and interpret, it can
leave the user guessing as to how useful the multiplier actually is
at low output levels, those approaching the specified error limit
(in this case) 100 mV.
The AD538’s error sources do not follow the percent of full-
scale approach to specification, thus it more optimally fits the
needs of the very wide dynamic range applications for which it is
best suited. Rather than as a percent of full scale, the AD538’s
error as a multiplier or divider for a 100:1 (100 mV to 10 V)
input range is specified as the sum of two error components: a
percent of reading (ideal output) term plus a fixed output offset.
Following this format the AD538AD, operating as a multiplier
or divider with inputs down to 100 mV, has a maximum error of1% of reading –500 mV. Some sample total error calculations
for both grades over the 100:1 input range are illustrated in the
chart below. This error specification format is a familiar one to
designers and users of digital voltmeters where error is specified
as a percent of reading – a certain number of digits on the meter
readout.
For operation as a multiplier or divider over a wider dynamic
range (>100:1), the AD538 has a more detailed error specifica-
tion that is the sum of three components: a percent of reading
term, an output offset term and an input offset term for the
VY/VX log ratio section. A sample application of this specifica-
tion, taken from Table I, for the AD538AD with VY = 1V, VZ =
100 mV and VX = 10 mV would yield a maximum error of2.0% of reading –500 mV –(1 V + 100 mV)/10 mV · 250 mV
or –2.0% of reading –500 mV – 27.5 mV. This example illus-
trates that with very low level inputs the AD538’s incremental
gain (VY + VZ)/VX has increased to make the input offset contri-
bution to error substantial.
Table I.Sample Error Calculation Chart (Worst Case)Total Error =
Total Error =
AD538
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGSSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 250 mW
Output Short Circuit-to-Ground . . . . . . . . . . . . . . . Indefinite
Input Voltages VX, VY, VZ . . . . . . . . . . . . . (+VS – 1 V), –1 V
Input Currents IX, IY, IZ, IO . . . . . . . . . . . . . . . . . . . . . . 1 mA
Operating Temperature Range . . . . . . . . . . . –25°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Storage . . . . . . . . . . . . . . 60 sec, +300°C
Thermal ResistanceJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/WJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
PIN CONFIGURATION
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD538 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TOTAL % OF READING ERROR
TEMPERATURE – 8C
OUTPUT STAGE OFFSET – Figure 1.Multiplier Error vs. Temperature
(100 mV < VX, VY, VZ £ 10V)
TEMPERATURE – 8C
TOTAL % OF READING ERROR
OUTPUT STAGE OFFSET –
200 Figure 2.Divider Error vs. Temperature
(100 mV < VX, VY, VZ £ 10 V)
Figure 3.VZ Feedthrough vs. Frequency
Figure 4.Small Signal Bandwidth vs. Denominator
Voltage (One-Quadrant Mult/Div)
TOTAL % OF READING ERROROUTPUT STAGE OFFSET –
TEMPERATURE – 8C
1200Figure 5.Multiplier Error vs. Temperature
(10 mV < VX, VY, VZ £ 100 mV)
Figure 6.Divider Error vs. Temperature
(10 mV < VX, VY, VZ £ 100 mV)
AD538
+10V
–VS
+VS
+2V
PWR
GND
SIGNAL
GNDFigure 9.Functional Block Diagram
FUNCTIONAL DESCRIPTIONAs shown in Figures 9 and 10, the VZ and VX inputs connect
directly to the AD538’s input log ratio amplifiers. This subsec-
tion provides an output voltage proportional to the natural log
of input voltage VZ, minus the natural log of input voltage VX.
The output of the log ratio subsection at B can be expressed by
the transfer function:
wherek = 1.3806 · 10–23 J/K,
q = 1.60219 · 10–19 C,is in Kelvins.
The log ratio configuration may be used alone, if correctly tem-
perature compensated and scaled to the desired output level
(see Applications section).
Under normal operation, the log-ratio output will be directly
connected to a second functional block at input C, the antilog
subsection. This section performs the antilog according to the
transfer function:
As with the log-ratio circuit included in the AD538, the user
may use the antilog subsection by itself. When both subsections
are combined, the output at B is tied to C, the transfer function
of the AD538 computational unit is:
which reduces to:
Finally, by increasing the gain, or attenuating the output of the
log ratio subsection via resistor programming, it is possible to
raise the quantity VZ/VX to the mth power. Without external
programming, m is unity. Thus the overall AD538 transfer
function equals:
where 0.2 < m < 5.
When the AD538 is used as an analog divider, the VY input can
be used to multiply the ratio VZ/VX by a convenient scale factor.
The actual multiplication by the VY input signal is accomplished
by adding the log of the VY input signal to the signal at C, which
is already in the log domain.
INPUT FREQUENCY – Hz
0.110k100k1M
IN mV PEAK-TO-PEAKFigure 7.VY Feedthrough vs. Frequency
DC OUTPUT VOLTAGE – Volts
VOLTAGE NOISE, e
–
Hz10
VX = 10VFigure 8.1 kHz Output Noise Spectral Density vs. DC Output
Voltage
