AD5384BBC-3 ,40-Channel, 3 V/5 V Single Supply,14-Bit, Serial Voltage-Output DACAPPLICATIONS Serial (SPI-®/QSPI-™/MICROWIRE-™/DSP-compatible, Variable optical attenuators (VOA) fe ..
AD5384BBC-5 ,40-Channel, 3 V/5 V Single Supply,14-Bit, Serial Voltage-Output DACCharacteristics ....... 18 Toggle Mode Function 32 Functional Description ... 21 Thermal Monitor Fu ..
AD538AD ,Real-Time Analog Computational Unit ACUSPECIFICATIONSS A AD538AD AD538BD AD538SDParameters Conditions Min Typ Max Min Typ Max Min Typ Max ..
AD538ADZ , Real-Time Analog Computational Unit (ACU)
AD538BD ,Real-Time Analog Computational Unit ACUCHARACTERISTICSOffset Voltage V = 0, V = –600 mV – 200 6500 – 100 6250 – 200 6500 m VY CT = T to T ..
AD538BD ,Real-Time Analog Computational Unit ACUFEATURESm
AD5384BBC-3-AD5384BBC-5
40-Channel, 3 V/5 V Single Supply,14-Bit, Serial Voltage-Output DAC
40-Channel, 3 V/5 V, Single-Supply,
Serial, 14-Bit Voltage Output DAC
Rev. A
FEATURES
Guaranteed monotonic
INL error: ±4 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down
Package type: 100-lead CSPBGA (10 mm × 10 mm)
User Interfaces:
Serial (SPI-®/QSPI-™/MICROWIRE-™/DSP-compatible,
featuring data readback) 2C-®compatible
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Variable optical attenuators (VOA)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8RESET
BUSY
CLR
DIN/SDA
SPI/I2C
SCLK/SCL
SYNC/AD 0
DCEN/AD 1
SDO
VOUT39/MON_OUTLDAC
VOUT38
DVDD (×3)DGND (×4)AVDD (×5)AGND (×5)DAC GND (×5)REFGNDREFOUT/REFINSIGNAL GND (×5)
Figure 1.
TABLE OF CONTENTS General Description.........................................................................3
Specifications.....................................................................................4
AD5384-5 Specifications.............................................................4
AC Characteristics........................................................................6
AD5384-3 Specifications.............................................................7
AC Characteristics........................................................................9
Timing Characteristics...................................................................10
Serial Interface............................................................................10 2C Serial Interface......................................................................12
Absolute Maximum Ratings..........................................................13
Pin Configuration and Function Descriptions...........................14
Terminology....................................................................................17
Typical Performance Characteristics...........................................18
Functional Description..................................................................21
DAC Architecture—General.....................................................21
Data Decoding............................................................................21
On-Chip Special Function Registers (SFR)............................22
SFR Commands..........................................................................22
Hardware Functions.......................................................................25
Reset Function............................................................................25
Asynchronous Clear Function..................................................25
BUSY and LDAC Functions......................................................25
Power-On Reset..........................................................................25
Power-Down...............................................................................25
Interfaces..........................................................................................26
DSP-, SPI-, Microwire-Compatible Serial Interfaces............26 2C Serial Interface.....................................................................28
Microprocessor Interfacing.......................................................31
Application Information................................................................32
Power Supply Decoupling.........................................................32
Monitor Function.......................................................................32
Toggle Mode Function...............................................................32
Thermal Monitor Function.......................................................33
AD5384 in a MEMS-Based Optical Switch............................33
Optical Attenuators....................................................................34
Outline Dimensions.......................................................................35
Ordering Guide..........................................................................35
REVISION HISTORY
10/04—Changed from Rev. 0 to Rev. A Changes to Table 19........................................................................24
Changes to Ordering Guide..........................................................35
7/04—Revision 0: Initial Version GENERAL DESCRIPTION The AD5384 is a complete single-supply, 40-channel, 14-bit
DAC available in a 100-lead CSPBGA package. All 40 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5384 includes an internal 1.25 V/2.5 V, 10 ppm/°C
reference, an on-chip channel monitor function that multiplexes
the analog outputs to a common MON_OUT pin for external
monitoring, and an output amplifier boost mode that allows the
amplifier slew rate to be optimized. The AD5384 contains a
serial interface compatible with SPI, QSPI, MICROWIRE, and
DSP interface standards with interface speeds in excess of
30 MHz and an I2C-compatible interface supporting 400 kHz
data transfer rate. An input register followed by a DAC register
provides double buffering, allowing the DAC outputs to be
updated independently or simultaneously. using the LDAC
input. Each channel has a programmable gain and offset adjust
register letting the user fully calibrate any DAC channel. Power
consumption is typically 0.25 mA/channel with boost mode off.
Table 1. Complete Family of High Channel Count, Low Voltage, Single-Supply DACs in Portfolio
Table 2. 40-Channel, Bipolar Voltage Output DAC
SPECIFICATIONS
AD5384-5 SPECIFICATIONS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications TMIN to TMAX, unless
otherwise noted.
Table 3.
1 AD5384-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV.
3 Guaranteed by characterization, not production tested. Default on the AD5384-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5384 control register; operating the AD5384-5 with a 1.25 V reference will lead to
degraded accuracy specifications.
AC CHARACTERISTICS1AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V.
Table 4. 1 Guaranteed by design and characterization, not production tested. The slew rate can be programmed via the current boost control bit (CR11) in the AD5384 control register.
AD5384-3 SPECIFICATIONS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications TMIN to TMAX,
unless otherwise noted.
Table 5.
AD5384-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C.
2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. Guaranteed by characterization, not production tested.
4 Default on the AD5384-3 is 1.25 V. Programmable to 2.5 V via CR12 in the AD5384 control register; operating the AD5384-3 with a 2.5 V reference will lead to degraded
accuracy specifications and limited input code range.
AC CHARACTERISTICS1AVDD = 2.7 V to 3.6 V and 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.
Table 6. 1 Guaranteed by design and characterization, not production tested. The slew rate can be programmed via the current boost control bit (CR11 ) in the AD5384 control register.
TIMING CHARACTERISTICS
SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX,
unless otherwise noted.
Table 7. Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD), and are timed from a voltage level of 1.2 V. See , F, and . Figure 2igure 3Figure 5,Figure 6
4 Standalone mode only. Daisy-chain mode only.
50pFVOH (MIN) OR
VOL (MAX)
200µA
200µA
IOL
IOH04652-0-003
Figure 2. Load Circuit for Digital Output Timing
1LDAC ACTIVE DURING BUSY
2LDAC ACTIVE AFTER BUSY
BUSY
SYNC
LDAC1
LDAC2
CLR
VOUT
VOUT2
VOUT1
DIN
SCLKFigure 3. Serial Interface Timing Diagram (Standalone Mode)
t7ASCLK
SYNC
DIN
SDO
INPUT WORD SPECIFIES
REGISTER TO BE READ
UNDEFINED
NOP CONDITION
SELECTED REGISTER
DATA CLOCKED OUT03731-0-005
Figure 4. Serial Interface Timing Diagram (Data Readback Mode)
SCLK
SYNC
DIN
SDO
LDAC04652-0-005
2C SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX,
unless otherwise noted.
Table 8. 1 See . Figure 6 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge. Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION04652-0-006
Figure 6. I 2C-Compatible Serial Interface Timing Diagram
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.1
Table 9. Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW
123456789101112
Figure 7. 100-Lead CSPBGA Pin Configuration
Table 10. Pin Number and Name
CSPBGA Table 11. Pin Function Descriptions
TERMINOLOGY
Relative Accuracy Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error, and is
expressed in LSB.
Differential Nonlinearity Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Zero-Scale Error Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register. Ideally, with all 0s loaded to
the DAC and m = all 1s, c = 2n – 1
VOUT(Zero-Scale) = 0 V
Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal), expressed in mV. It is mainly due to
offsets in the output amplifier.
Offset Error Offset error is a measure of the difference between VOUT
(actual) and VOUT (ideal) in the linear region of the transfer
function, expressed in mV. Offset error is measured on the
AD5384-5 with Code 32 loaded into the DAC register, and on
the AD5384-3 with Code 64.
Gain Error Gain Error is specified in the linear region of the output range
between VOUT = 10 mV and VOUT = AVDD – 50 mV. It is the
deviation in slope of the DAC transfer characteristic from the
ideal and is expressed in %FSR with the DAC output unloaded.
DC Crosstalk This is the dc change in the output level of one DAC at midscale
in response to a full-scale code (all 0s to all 1s, and vice versa)
and output change of all other DACs. It is expressed in LSB.
DC Output Impedance This is the effective output source resistance. It is dominated by
package lead resistance.
Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change,
and is measured from the BUSY rising edge.
Digital-to-Analog Glitch Energy This is the amount of energy injected into the analog output at
the major code transition. It is specified as the area of the glitch
in nV-s. It is measured by toggling the DAC register data
between 0x1FFF and 0x2000.
DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one DAC due to both the digital change and the sub-
sequent analog output change at another DAC. The victim
channel is loaded with midscale. DAC-to-DAC crosstalk is
specified in nV-s.
Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output
of one converter due to a change in the DAC register code of
another converter. It is specified is specified in nV-s.
Digital Feedthrough When the device is not selected, high frequency logic activity
on the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the VOUT
pins. It can also be coupled along the supply and ground lines.
This noise is digital feedthrough.
Output Noise Spectral Density This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per √Hertz).
It is measured by loading all DACs to midscale and measuring
noise at the output. It is measured in nV/√Hz in a 1 Hz band-
width at 10 kHz.
TYPICAL PERFORMANCE CHARACTERISTICS 03731-0-033
INPUT CODE
INL E
RROR (LS
–1.5Figure 8. Typical AD5384-5 INL Plot
03731-0-034
SAMPLE NUMBER
AMP
ITUDE
(V
2.524Figure 9. AD5384-5 Glitch Impulse
Figure 10. Slew Rate with Boost Off
03731-0-035
INPUT CODE
INL E
RROR (LS
–1.5Figure 11. Typical AD5384-3 INL Plot
03731-0-048
REFERENCE DRIFT (ppm/°C)
FRE
NCYFigure 12. AD5384-REFOUT Temperature Coefficient
Figure 13. Slew Rate with Boost On
