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AD5382BST-3-AD5382BST-5
32-Channel 14-Bit 3 V/5 V Single-Supply Voltage-Output DAC
32-Channel, 3 V/5 V, Single-Supply,
14-Bit, Voltage Output DAC
Rev. 0
FEATURES
Guaranteed monotonic
INL error: ±4 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm × 14 mm)
User Interfaces:
Parallel
Serial (SPI®/QSPI™/MICROWIRE™/DSP compatible,
featuring data readback) 2C® compatible
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user programmable code
Amplifier boost mode to optimize slew rate
User programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Variable optical attenuators (VOA)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8DB13/(DIN/SDA)
DB12/(SCLK/SCL)
DB11/(SPI/I2C)
DB10
REG 0
REG 1
RESET
BUSY
CLR
MON_IN1
MON_IN2
MON_IN3
MON_IN4
SER/PAR
FIFO EN
CS/(SYNC/AD0)
WR/(DCEN/AD1)
SDO
MON_OUTLDAC
VOUT31
DVDD (×3)DGND (×3)AVDD (×4)AGND (×4)DAC GND (×4)REFGNDREFOUT/REFINSIGNAL GND (×4)
DB0
Figure 1.
TABLE OF CONTENTS General Description.........................................................................3
Specifications.....................................................................................4
AD5382-5 Specifications.............................................................4
AD5382-3 Specifications.............................................................6
AC Characteristics........................................................................7
Timing Characteristics.....................................................................8
SPI, QSPI, MICROWIRE, or DSP Compatible Serial
Interface....................................................................................8 2C Serial Interface......................................................................10
Parallel Interface.........................................................................11
Absolute Maximum Ratings..........................................................13
Pin Configuration and Function Descriptions...........................14
Terminology....................................................................................17
Typical Performance Characteristics...........................................18
Functional Description..................................................................21
DAC Architecture—General.....................................................21
Data Decoding............................................................................21
On-Chip Special Function Registers (SFR)............................22
SFR Commands..........................................................................22
Hardware Functions.......................................................................25
Reset Function............................................................................25
Asynchronous Clear Function..................................................25
BUSY and LDAC Functions......................................................25
FIFO Operation in Parallel Mode............................................25
Power-On Reset..........................................................................25
Power-Down...............................................................................25
AD5382 Interfaces..........................................................................26
DSP, SPI, Microwire Compatible Serial Interfaces.................26 2C Serial Interface.....................................................................28
Parallel Interface.........................................................................30
Microprocessor Interfacing.......................................................31
Application Information................................................................33
Power Supply Decoupling.........................................................33
Typical Configuration Circuit..................................................33
AD5382 Monitor Function.......................................................34
Toggle Mode Function...............................................................34
Thermal Monitor Function.......................................................35
AD5382 in a MEMS Based Optical Switch.............................35
Optical Attenuators....................................................................36
Outline Dimensions.......................................................................37
Ordering Guide..........................................................................37
REVISION HISTORY 5/04—Revision 0: Initial Version
GENERAL DESCRIPTION The AD5382 is a complete, single-supply, 32-channel, 14-bit
DAC available in a 100-lead LQFP package. All 32 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5382 includes an internal software-selectable 1.25 V/
2.5 V, 10 ppm/°C reference, an on-chip channel monitor
function that multiplexes the analog outputs to a common
MON_OUT pin for external monitoring, and an output
amplifier boost mode that allows optimization of the amplifier
slew rate. The AD5382 contains a double-buffered parallel
interface that features a 20 ns WR pulse width, an SPI/QSPI/
MICROWIRE/DSP compatible serial interface with interface
speeds in excess of 30 MHz and an I2C compatible interface
that supports a 400 kHz data transfer rate.
An input register followed by a DAC register provides double
buffering, allowing the DAC outputs to be updated indepen-
dently or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjust
register that allows the user to fully calibrate any DAC channel.
Power consumption is typically 0.25 mA/channel when
operating with boost mode disabled.
Table 1. Other High Channel Count, Low Voltage, Single Supply DACs in Product Portfolio
Table 2. 40-Channel Bipolar Voltage Output DAC SPECIFICATIONS
AD5382-5 SPECIFICATIONS
Table 3. AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V;
External REFIN = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted
1 AD5382-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV.
3 Guaranteed by characterization, not production tested. Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded
accuracy specifications.
AD5382-3 SPECIFICATIONS
Table 4. AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V;
all specifications TMIN to TMAX, unless otherwise noted AD5382-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C.
2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. Guaranteed by characterization, not production tested.
4 Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded
accuracy specifications.
AC CHARACTERISTICS1
Table 5. AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND= 0 V Guaranteed by design and characterization, not production tested.
2 The slew rate can be programmed via the current boost control bit (CR11 ) in the AD5382 control register.
TIMING CHARACTERISTICS
SPI, QSPI, MICROWIRE, OR DSP COMPATIBLE SERIAL INTERFACE
Table 6. DVDD= 2.7 V to 5.5 V ; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
TMIN to TMAX, unless otherwise noted Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.2 V. See Figure 2, Figure 3, Figure 4, and Figure 5. Standalone mode only. Daisy-chain mode only.
50pFVOH (MIN) OR
VOL (MAX)
200µA
200µA
IOL
IOH03731-0-003
Figure 2. Load Circuit for SDO Timing Diagram
(Serial Interface, Daisy-Chain Mode)
1LDAC ACTIVE DURING BUSY
2LDAC ACTIVE AFTER BUSY
BUSY
SYNC
LDAC1
LDAC2
CLR
VOUT
VOUT2
VOUT1
DIN
SCLKFigure 3. Serial Interface Timing Diagram (Standalone Mode)
t7ASCLK
SYNC
DIN
SDO
INPUT WORD SPECIFIES
REGISTER TO BE READ
UNDEFINED
NOP CONDITION
SELECTED REGISTER
DATA CLOCKED OUT03731-0-005
Figure 4. Serial Interface Timing Diagram (Data Readback Mode)
t13
SCLK
SYNC
SDO
DIN
LDAC03731-0-006
2C SERIAL INTERFACE Table 7. DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
TMIN to TMAX, unless otherwise noted 1 Guaranteed by design and characterization, not production tested. See Figure 6.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4 Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITIONt703731-0-007
Figure 6. I2C Compatible Serial Interface Timing Diagram
PARALLEL INTERFACE
Table 8. DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
TMIN to TMAX, unless otherwise noted 1 Guaranteed by design and characterization, not production tested. All input signals are specified with tR = tR = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
3 See Figure 7. See Figure 29.
5 Measured with the load circuit of Figure 2.
REG0, REG1, A4..A0
DB13..DB0
BUSY
LDAC1
VOUT1
VOUT2
CLR
VOUT
LDAC2
2LDAC ACTIVE AFTER BUSY03731-0-008
Figure 7. Parallel Interface Timing Diagram
ABSOLUTE MAXIMUM RATINGS
Table 9. TA = 25°C, unless otherwise noted1 1 Transient currents of up to 100 mA will not cause SCR latch-up
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NCNCNC
VOU
VOU
VOUNC
VOU
VOU
VOU
VOU
VOU
DAC_
GND2
IGNAL_
ND2
VOU
VOU
VOU
NC/AD0
IN/SDA)
CLK/S
SPI/I2C)
N/AD1
FIFO EN
CLR
VOUT24
VOUT25
VOUT26
VOUT27
SIGNAL_GND4
DAC_GND4
AGND4
AVDD4
VOUT28
VOUT29
VOUT30
VOUT31
REF GND
REFOUT/REFIN
SIGNAL_GND1
DAC_GND1
AVDD1
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
AGND103733-0-002
Figure 8. 100-Lead LQFP Pin Configuration
Table 10. Pin Function Descriptions
TERMINOLOGY
Relative Accuracy Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error, and is
expressed in LSB.
Differential Nonlinearity Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Zero-Scale Error Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register. Ideally, with all 0s loaded to
the DAC and m = all 1s, c = 2n – 1:
VOUT(Zero-Scale) = 0 V
Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal), expressed in mV. It is mainly due to
offsets in the output amplifier.
Offset Error Offset error is a measure of the difference between VOUT
(actual) and VOUT (ideal) in the linear region of the transfer
function, expressed in mV. Offset error is measured on the
AD5382-5 with Code 32 loaded into the DAC register, and on
the AD5382-3 with Code 64.
Gain Error Gain Error is specified in the linear region of the output range
between VOUT = 10 mV and VOUT = AVDD – 50 mV. It is the
deviation in slope of the DAC transfer characteristic from the
ideal and is expressed in %FSR with the DAC output unloaded.
DC Crosstalk This is the dc change in the output level of one DAC at midscale
in response to a full-scale code (all 0s to all 1s, and vice versa)
and output change of all other DACs. It is expressed in LSB.
DC Output Impedance This is the effective output source resistance. It is dominated by
package lead resistance.
Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change,
and is measured from the BUSY rising edge.
Digital-to-Analog Glitch Energy This is the amount of energy injected into the analog output at
the major code transition. It is specified as the area of the glitch
in nV-s. It is measured by toggling the DAC register data
between 0x1FFF and 0x2000.
DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one DAC due to both the digital change and to the
subsequent analog output change at another DAC. The victim
channel is loaded with midscale. DAC-to-DAC crosstalk is
specified in nV-s.
Digital Crosstalk The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter
is defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.
Output Noise Spectral Density This is a measure of internally generated random noise.
Random noise is characterized as a spectral density (voltage per
√Hertz). It is measured by loading all DACs to midscale and
measuring noise at the output. It is measured in nV/√Hz in a
1 Hz bandwidth at 10 kHz.
TYPICAL PERFORMANCE CHARACTERISTICS 03731-0-033
INPUT CODE
INL E
RROR (LS
–1.5Figure 9. Typical AD5382-5 INL Plot
03731-0-034
SAMPLE NUMBER
AMP
ITUDE
(V
2.524Figure 10. AD5382-5 Glitch Impulse
Figure 11. Slew Rate with Boost Off
03731-0-035
INPUT CODE
INL E
RROR (LS
–1.5Figure 12. Typical AD5382-3 INL Plot
03731-0-036
SAMPLE NUMBER
AMP
ITUDE
(V
1.246Figure 13. AD5382-3 Glitch Impulse
Figure 14. Slew Rate with Boost On
04598-0-049
AIDD (mA)8910
RCE
NTAGE
OF UNITS
(%)Figure 15. AIDD Histogram
04598-0-050
DIDD (mA)
NUMBE
R OF UNITSFigure 16. DIDD Histogram
Figure 17. Exiting Soft Power Down
Figure 18. AD5382 Power-Up Transient
04598-0-051
INL ERROR DISTRIBUTION (LSB)–2–101
NUMBE
R OF UNITSFigure 19. INL Error Distribution
Figure 20. Exiting Hardware Power Down
03731-0-039
CURRENT (mA)
OUT
(VFigure 21. AD5382-5 Output Amplifier Source and Sink Capability
03731-0-047
ISOURCE/ISINK (mA)
RROR V
LTAGE
(V
–0.15Figure 22. Headroom at Rails vs. Source/Sink Current
03731-0-047
FREQUENCY (Hz)
100k1001k10k
OUTP
UT NOIS
(nV
100Figure 23 REFOUT Noise Spectral Density
03731-0-040
CURRENT (mA)
OUT
(VFigure 24. AD5382-3 Output Amplifier Source and Sink Capability
03731-0-041
SAMPLE NUMBER
AMP
ITUDE
(V
2.450Figure 25. Adjacent Channel DAC-to-DAC Crosstalk
Figure 26. 0.1 Hz to 10 Hz Noise Plot
