AD537JH ,Integrated Circuit Voltage-to-Frequency ConverterApplications REF R SVREF5 CAP MIL-STD-883 Compliant Versions Available–VS(CONNECTED TO CASE)PRODUCT ..
AD537JH ,Integrated Circuit Voltage-to-Frequency ConverterApplications REF R SVREF5 CAP MIL-STD-883 Compliant Versions Available–VS(CONNECTED TO CASE)PRODUCT ..
AD537KD ,Integrated Circuit Voltage-to-Frequency Converterapplications section. To maintain normal operation,these outputs should be operated into the extern ..
AD537KH ,Integrated Circuit Voltage-to-Frequency ConverterFEATURES PIN CONFIGURATIONS Low Cost A–D Conversion D-14 Package H- ..
AD537SD ,Integrated Circuit Voltage-to-Frequency ConverterSpecifications same as AD537K.1Nonlinearity is specified for a current input level (I ) to the conv ..
AD537SH ,Integrated Circuit Voltage-to-Frequency Converterspecifications, refer to Analog Devices Military Products Databook.
AD9432BST-105 ,12-Bit, 80 MSPS/105 MSPS A/D ConverterSpecifications subject to change without notice.*Stresses above those listed under Absolute Maximum ..
AD9432BST-105 ,12-Bit, 80 MSPS/105 MSPS A/D ConverterSPECIFICATIONSTest AD9432BST-80 AD9432BST-105Parameter Temp Level Min Typ Max Min Typ Max UnitRESOL ..
AD9433BSQ-105 ,12-Bit, 105 MSPS/125 MSPS IF Sampling A/D ConverterSPECIFICATIONS (V = 3.3 V, V = 5 V; internal reference; differential encode input, unless otherwise ..
AD9433BSQ-125 ,12-Bit, 105 MSPS/125 MSPS IF Sampling A/D ConverterSPECIFICATIONS (V = 3.3 V, V = 5 V; differential encode input, unless otherwise noted.)DD CCTest AD ..
AD9433BSQ-125 ,12-Bit, 105 MSPS/125 MSPS IF Sampling A/D ConverterAPPLICATIONSCellular Infrastructure Communication Systems3G Single and Multicarrier ReceiversIF Sam ..
AD9433BSVZ-105 , 12-Bit, 105 MSPS/125 MSPS, IF Sampling ADC
AD537JD-AD537JH-AD537KD-AD537KH-AD537SD-AD537SH
Integrated Circuit Voltage-to-Frequency Converter
REV.C
Integrated Circuit
Voltage-to-Frequency Converter
PRODUCT DESCRIPTIONThe AD537 is a monolithic V-F converter consisting of an input
amplifier, a precision oscillator system, an accurate internal ref-
erence generator and a high current output stage. Only a single
external RC network is required to set up any full-scale (F.S.)
frequency up to 100kHz and any F.S. input voltage up to30V. Linearity error is as low as ±0.05% for 10kHz F.S., and
operation is guaranteed over an 80dB dynamic range. The over-
all temperature coefficient (excluding the effects of external
components) is typically ±30ppm/°C. The AD537 operates
from a single supply of 5V to 36V and consumes only 1.2mA
quiescent current.
A temperature-proportional output, scaled to 1.00mV/K,
enables the circuit to be used as a reliable temperature-to-
frequency converter; in combination with the fixed reference
output of 1.00V, offset scales such as 0°C or 0°F can be generated.
The low drift (1µV/°C typ) input amplifier allows operation
directly from small signals (e.g., thermocouples or strain gages)
while offering a high (250MΩ) input resistance. Unlike most
V–F converters, the AD537 provides a square-wave output, and
can drive up to 12 TTL loads, LEDs, very long cables, etc.
The excellent temperature characteristics and long-term stability
of the AD537 are guaranteed by the primary bandgap reference
generator and the low T.C. silicon chromium thin film resistors
used throughout.
The device is available in either a 14-lead ceramic DIP or a 10-lead
metal can; both are hermetically sealed packages.
*Protected by Patent Nos. 3,887,963 and RE 30,586.
FEATURES
Low Cost A–D Conversion
Versatile Input AmplifierPositive or Negative Voltage ModesNegative Current ModeHigh Input Impedance, Low Drift
Single Supply, 5V to 36V
Linearity: �0.05% FS
Low Power: 1.2mA Quiescent Current
Full-Scale Frequency up to 100kHz
1.00V Reference
Thermometer Output (1mV/K)
F-V Applications
MIL-STD-883 Compliant Versions Available
PIN CONFIGURATIONS
D-14 Package H-10A PackageThe AD537 is available in three performance/temperature
grades; the J and K grades are specified for operation over the
0°C to +70°C range while the AD537S is specified for operation
over the extended temperature range, –55°C to +125°C.
PRODUCT HIGHLIGHTS1. The AD537 is a complete V-F converter requiring only an
external RC timing network to set the desired full-scale fre-
quency and a selectable pull-up resistor for the open collec-
tor output stage. Any full-scale input voltage range from
100mV to 10 volts (or greater, depending on +VS) can be
accommodated by proper selection of timing resistor. The
full-scale frequency is then set by the timing capacitor from
the simple relationship, f = V/10RC.The power supply requirements are minimal, only 1.2mA
quiescent current is drawn from a single positive supply from
4.5volts to 36 volts. In this mode, positive inputs can vary
from 0 volts (ground) to (+VS – 4) volts. Negative inputs can
easily be connected for below ground operation.F-V converters with excellent characteristic are also easy to
build by connecting the AD537 in a phase-locked loop. Ap-
plication particulars are shown in Figure 6.The versatile open-collector NPN output stage can sink up
to 20mA with a saturation voltage less than 0.4 volts. The
Logic Common terminal can be connected to any level be-
tween ground (or –VS) and 4 volts below +VS. This allows
easy direct interface to any logic family with either positive or
negative logic levels.The AD537 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Product
Databook or current AD537/883B data sheet for detailed
specifications.
AD537–SPECIFICATIONS(typical @ +25�C with VS (total) = 5 V to 36 V, unless otherwise noted)REFERENCE OUTPUTS
OUTPUT INTERFACE (Open Collector Output)
PACKAGE OPTIONS
NOTES
*Specifications same as AD537JH.**Specifications same as AD537K.Nonlinearity is specified for a current input level (IIN) to the converter from 0.1µA to 1000µA. Converter has 100% overrange capability up to IIN = 2000µA with slightly
reduced linearity. Nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a percentage of full scale.Guaranteed not tested.Maximum voltage input level is equal to the supply on either input terminal. However, large negative voltage levels can be applied to the negative terminal if the input is scaled to
a nominal 1mA full scale through an appropriate value resistor (See Figure 2).Loading the 1.0 volt or 1mV/K outputs can cause a significant change in overall circuit performance, as indicated in the applications section. To maintain normal operation,
CIRCUIT OPERATIONBlock diagrams of the AD537 are shown above. A versatile
operational amplifier (BUF) serves as the input stage; its pur-
pose is to convert and scale the input voltage signal to a drive
current in the NPN follower. Optimum performance is achieved
when, at the full-scale input voltage, a 1mA drive current is
delivered to the current-to-frequency converter. The drive cur-
rent to the current-to-frequency converter (an astable
multivibrator) provides both the bias levels and the charging
current to the externally connected timing capacitor. This
“adaptive” bias scheme allows the oscillator to provide low non-
linearity over the entire current input range of 0.1µA to
2000µA. The square wave oscillator output goes to the output
driver which provides a floating base drive to the NPN power
transistor. This floating drive allows the logic interface to be ref-
erenced to a different level than –VS. The “SYNC” input (“D”
package only) allows the oscillator to be slaved to an external
master oscillator; this input can also be used to shut off the
oscillator.
The reference generator uses a bandgap circuit (this allows
single-supply operation to 4.5 volts which is not possible with
low T.C. Zeners) to provide the reference and bias levels for the
amplifier and oscillator stages. The reference generator also pro-
vides the precision, low T.C. 1.00 volt output and the VTEMP
output which tracks absolute temperature at 1mV/K.
V-F CONNECTION FOR POSITIVE INPUT VOLTAGESThe positive voltage input range is from –VS (ground in single
supply operation) to 4 volts below the positive supply. The con-
nection shown in Figure 1 provides a very high (250MΩ) input
impedance. The input voltage is converted to the proper drive
current at Pin 3 by selecting a scaling resistor. The full-scale
current is 1mA, so, for example a 10 volt range would require a
nominal 10kΩ resistor. The trim range required will depend on
capacitor tolerance. Full-scale currents other than 1mA can be
chosen, but linearity will be reduced; 2mA is the maximum
allowable drive.
As indicated by the scaling relationship in Figure 1, a 0.01µF
timing capacitor will give a 10kHz full-scale frequency, and
0.001µF will give 100kHz with a 1mA drive current. The
maximum frequency is 150kHz. Polystyrene or NPO ceramic
capacitors are preferred for T.C. and dielectric absorption;
polycarbonate or mica are acceptable; other types will degrade
linearity. The capacitor should be wired very close to the
AD537.
V-F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE
OR CURRENTA wide range of negative input voltages can be accommodated
with proper selection of the scaling resistor, as indicated in Fig-
ure 2. This connection, unlike the buffered positive connection,
is not high impedance since the 1mA F.S. drive current must be
supplied by the signal source. However, very large negative volt-
ages beyond the supply can be handled easily; just modify the
scaling resistors appropriately. Diode CR1 (HP50822811) is
necessary for overload and latchup protection for current or
voltage inputs.
If the input signal is a true current source, R1 and R2 are not
used. Full-scale calibration can be accomplished by connecting a
200kΩ pot in series with a fixed 27kΩ from Pin 7 to –VS (see
calibration section, below).
Figure 2.V-F Connections for Negative Input Voltage or
Current
CALIBRATIONThere are two independent adjustments: scale and offset. The
first is trimmed by adjustment of the scaling resistor R and the
second by the (optional) potentiometer connected to +VS and
the VOS pins (“D” package only). Precise calibration requires the
use of an accurate voltage standard set to the desired FS value
and a frequency meter; a scope is useful for monitoring output
waveshape. Verification of linearity requires the availability of a
switchable voltage source (or a DAC) having a linearity error
below ±0.005%, and the use of long measurement intervals to
minimize count uncertainties. Every AD537 is automatically tested
for linearity, and it will not usually be necessary to perform this
verification, which is both tedious and time-consuming.
Although drifts are small it is good practice to allow the operat-
ing environment to attain stable temperature and to ensure that
the supply, source and load conditions are proper. Begin by set-
ting the input voltage to 1/10,000 of full scale. Adjust the offset
pot until the output frequency is 1/10,000 of full scale (for ex-
ample 1Hz for FS of 10kHz). This is most easily accomplished
using a frequency meter connected to the output. Then apply
the FS input voltage and adjust the gain pot until the desired FS
frequency is indicated. In applications where the FS input is
small, this adjustment will very slightly affect the offset voltage,
due to the input bias current of the buffer amplifier. A change of
lkΩ in R will affect the input by approximately 100µV, which is
as much as 0.1% of a 100mV FS range. Therefore, it may be
AD537The –VIN, +VIN and IIN pins should not be driven more than
300mV below –VS. This would cause internal junctions to con-
duct, possibly damaging the IC. The AD537 can be protected
from “below –VS” inputs by a Schottky diode, CR1 (HP5082-
2811) as shown in Figure 3. It is also desirable not to drive
+VIN, –VIN and IIN above +VS. In operation, the converter will
become very nonlinear for inputs above (+VS – 3.5V). Control
currents above 2mA will also cause nonlinearity.
The 80 dB dynamic range of the AD537 guarantees operation
from a control current of 1mA (nominal FS) down to 100nA
(equivalent to 1mV to 10V FS). Below 100nA improper op-
eration of the oscillator may result, causing a false indication of
input amplitude. In many cases this might be due to short-lived
noise spikes which become added to the input. For example,
when scaled to accept a FS input of 1 V, the –80dB level is
only 100µV, so when the mean input is only 60dB below FSmV), noise spikes of 0.9mV are sufficient to cause momen-
tary malfunction.
This effect can be minimized by using a simple low-pass filter
ahead of the converter and a guard ring around the IIN or –VIN
pins. For a FS of 10kHz a single-pole filter with a time-constant
of 100ms (Figure 2) will be suitable, but the optimum configu-
ration will depend on the application and type of signal process-
ing. Noise spikes are only likely to be a cause of error when the
input current remains near its minimum value for long periods
of time; above 100nA (1mV) full integration of additive input
noise occurs.
The AD537 is somewhat susceptible to interference from other
signals. The most sensitive nodes (besides the inputs) are the
capacitor terminals and the SYNC pin. The timing capacitor
should be located as close as possible to the AD537 to minimize
signal pickup in the leads. In some cases, guard rings or shield-
ing may be required. The SYNC pin should be decoupled
through a 0.005µF (or larger) capacitor to Pin 13 (+VS). This
minimizes the possibility that the AD537 will attempt to syn-
chronize to a spurious signal. This precaution is unnecessary on
the metal can package since the SYNC function is not brought
out to a package pin and is thus not susceptible to pickup.
DECOUPLINGIt is good engineering practice to use bypass capacitors on the
supply-voltage pins and to insert small-valued resistors (10Ω to
100Ω) in the supply lines to provide a measure of decoupling
between the various circuits in a system. Ceramic capacitors of
0.1µF to 1.0µF should be applied between the supply-voltage
pins and analog signal ground for proper bypassing on the
AD537.
A decoupling capacitor may also be useful from +VS to SYNC
in those applications where very low cycle-to-cycle period varia-
tion (jitter) is demanded. By placing a capacitor across +VS and
SYNC this noise is reduced. On the 10kHz FS range, a 6.8µF
capacitor reduces the jitter to one in 20,000 which adequate for
most applications. A tantalum capacitor should be used to avoid
errors due to dc leakage.
In some cases the signal may be in the form of a negative cur-
rent source. This can be handled in a similar way to a negative
input voltage. However, the scaling resistor is no longer re-
quired, eliminating the capability of trimming full scale in this
fashion. Since it will usually be impractical to vary the capaci-
tance, an alternative calibration scheme is needed. This is
shown in Figure 3. A resistor-potentiometer connected from
the VR output to –VS will alter the internal operating conditions
in a predictable way, providing the necessary adjustment range.
With the values shown, a range of ±4% is available; a larger
range can be attained by reducing R1. This technique does not
degrade the temperature-coefficient of the converter, and the
linearity will be as for negative input voltages. The minimum
supply voltage may be used.
Unless it is required to set the input node at exactly ground
potential, no offset adjustment is needed. The capacitor C is se-
lected to be 5% below the nominal value; with R2 in its
midposition the output frequency is given by:
where f is in kHz, I is in mA and C is in µF. For example, for a
FS frequency of 10kHz at a FS input of 1mA, C = 9500pF.
Calibration is effected by applying the full-scale input and ad-
justing R2 for the correct reading.
This alternative adjustment scheme may also be used when it is
desired to present an exact input resistance in the negative volt-
age mode. The scaling relationship is then
The calibration procedure is then similar to that used for posi-
tive input voltages, except that the scale adjustment is by means
of R2.
27k
200k
+VS
IIN
10Cf =
VLOGIC
–VS
VOS
VOS
LOGIC GND
ADJ.
DEC/SYN
VTEMP
VREFFigure 3.Scale Adjustment for Current Inputs
INPUT PROTECTIONThe AD537 was designed to be used with a minimum of addi-
tional hardware. However, the successful application of a preci-
sion IC involves a good understanding of possible pitfalls and
NONLINEARITY SPECIFICATIONThe preferred method for specifying linearity error is in terms of
the maximum deviation from the ideal relationship after cali-
brating the converter at full scale and “zero”. This error will
vary with the full-scale frequency and the mode of operation.
The AD537 operates best at a 10kHz full-scale frequency with
a negative voltage input; the linearity is typically within ±0.05%.
Operating at higher frequencies or with positive inputs will
degrade the linearity as indicates in the Specification table. The
shape of a typical linearity plot is given in Figure 4.
10k1k100
OUTPUT FREQUENCY – Hz
NONLINEARITY
% OF FULL SCALE
0.02Figure 4a. Typical Nonlinearity Error Envelopes withkHz F.S. Output
100k10k1k
OUTPUT FREQUENCY – Hz
NONLINEARITY
% OF FULL SCALE
0.02Figure 4b. Typical Nonlinearity Error with 100kHz F.S.
Output
OUTPUT INTERFACING CONSIDERATIONSThe design of the output stage allows easy interfacing to all digi-
tal logic families. The collector and emitter of the output NPN
transistor are both uncommitted; the emitter can be tied to any
voltage between –VS and 4 volts below +VS. The open collector
can be pulled up to a voltage 36 volts above the emitter regard-
less of +VS. The high power output stage can supply up tomA (10mA for “H” package) at a maximum saturation volt-
age of 0.4 volts. The stage limits the output current at 25mA; it
Figure 5 shows the AD537 with a standard 0 to +10 volt input
connection and the output stage connections. The values for the
logic common voltage, pull-up resistor, positive logic level, and
–VS supply are given in the accompanying chart for several logic
forms.
Figure 5.Interfacing Standard Logic Families
APPLICATIONSThe diagrams and descriptions of the following applications are
provided to stimulate the discerning engineer with alternative
circuit design ideas. “Applications of the AD537 IC Voltage-
to-Frequency Converter”, available from Analog Devices on
request, covers a wider range of topics and concepts in data
conversion and data transmission using voltage-to-frequency
converters.
TRUE TWO-WIRE DATA TRANSMISSIONFigure 6 shows the AD537 in a true two-wire data transmission
scheme. The twisted-pair transmission lines serves the dual pur-
pose of supplying power to the device and also carrying fre-
quency data in the form of current modulation. The PNP circuit
at the receiving end represents a fairly simple way for converting
the current modulation back into a voltage square wave which
will drive digital logic directly. The 0.6 volt square wave which
will appear on the supply line at the device terminals does not
affect the performance of the AD537 because of its excellent
supply rejection. Also, note that the circuit operates at nearly
constant average power regardless of frequency.
GND
+VS
–VS
(CONNECTED TO CASE)
LINK
+15
3.3k
+VS
OUTPUTFigure 6.True Two-Wire Operation
AD537
F-V CONVERTERSThe AD537 can be used as a high linearity VCO in a phase-
locked loop to accomplish frequency-to-voltage conversion. By
operating the loop without a low-pass filter in the feedback path
(first-order system), it can lock to any frequency from zero to an
upper limit determined by the design, responding in three or
four cycles to a step change of input frequency. In practice, the
overall response time is determined by the characteristics of the
averaging filter which follows the PLL.
Figure 7 shows a connection using a low power TTL quad
open-collector nand gate which serves as the phase comparator.
The input signal should be a pulse train or square wave with
characteristics similar to TTL or 5-volt CMOS outputs. Any
duty cycle is acceptable, but the minimum pulse width is 40µs.
The output voltage is one volt for a 10kHz input frequency.
The output as shown here is at a fairly high impedance level; for
many situations an additional buffer may be required.
Trimming is similar to V-F application trimming. First set the
VOS trimmer to mid-scale. Apply a 10kHz input frequency and
trim the 2kΩ potentiometer for 1.00 volts out. Then apply aHz waveform and trim the VOS for 1mV out. Finally, retrim
the full-scale output at 10kHz. Other frequency scales can be
obtained by appropriate scaling of timing components.
Figure 7. 10kHz F-V Converter
TEMPERATURE-TO-FREQUENCY CONVERSIONThe linear temperature-proportional output of the AD537 can
be used as shown in these applications to perform various direct
temperature-to-frequency conversion functions; it can also be
used with other external connections in a temperature sensing
or compensation scheme. If the sensor output is used externally,
it should be buffered through an op amp since loading that
point will cause significant error in the sensor output as well as
in the main V-F converter circuitry.
An absolute temperature (Kelvin)-to-frequency converter is very
easily accomplished, as shown in Figure 8. The 1mV per K out-
put serves as the input to the buffer amplifier, which then scales
the oscillator drive current to a nominal 298µA at +25°C
(298K). Use of a 1000pF capacitor results in a corresponding
normally result in an accuracy of ±2°C from –55°C to +125°C
(using an AD537S). An NPO ceramic capacitor is recom-
mended to minimize nonlinearity due to capacitance drift.
Figure 8.Absolute Temperature to Frequency Converter
OFFSET TEMPERATURE SCALESMany other temperature scales can be set up by offsetting the
temperature output with the voltage reference output. Such a
scheme is shown by the Celsius-to-frequency converter in
Figure 9. Corresponding component values for a Fahrenheit-to-
frequency converter which give 10Hz/°F are given in parentheses.
fOUT
10Hz/°C
(10Hz/°F)
+5V
2.74k
(4.02k)
500Ω
3900 pF
(1500pF)Figure 9.Offset Temperature Scale Converters Centigrade
and (Fahrenheit) to Frequency
A simple calibration procedure which will provide ±2°C accu-
racy requires substitution of a 7.27k resistor for the series com-
bination of the 6.04k with the 2k trimmer; then simply set the
500Ω trimmer to give 250Hz at +25°C.
High accuracy calibration procedure:Measure room temperature in K.Measure temperature output at Pin 6 at that temperature.Calculate offset adjustment as follows:Temporarily disconnect 49Ω resistor (or 500Ω pot) and
trim 2kΩ pot to give the offset voltage at the indicated node.
Reconnect 49Ω resistor.Adjust slope trimmer to give proper frequency at room tem-
