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AD5379ABC
40-Channel 14-Bit Bipolar Voltage-Output D/A Converter
40-Channel, 14-Bit, Parallel and
Serial Input, Bipolar Voltage-Output DAC
Rev. 0
FEATURES
40-channel DAC in 13 mm × 13 mm 108-lead CSPBGA
Guaranteed monotonic to 14 bits
Buffered voltage outputs
Output voltage span of 3.5 V × VREF(+)
Maximum output voltage span of 17.5 V
System calibration function allowing user-programmable
offset and gain
Pseudo differential outputs relative to REFGND
Clear function to user-defined REFGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
DAC increment/decrement mode
Channel grouping and addressing features
Interface options:
Parallel interface
DSP/microcontroller-compatible 3-wire serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
SDO daisy-chaining option
Power-on reset
Digital reset (RESET pin and soft reset function)
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
FUNCTIONAL BLOCK DIAGRAM
VCCVDDVSSAGND
RESET
DGNDLDACVBIASVREF1(+)VREF1(–)REFGND A1
DCEN/WR
SYNC/CS
REG0
REG1
DB13
SCLK/DB12
DIN/DB11
DB0
SER/PAR
DIN
SCLK
SDO
FIFOEN
REFGND B1
REFGND B2
REFGND C1
REFGND C2
REFGND D1
REFGND D2
BUSYVREF2(+)VREF2(–)REFGND A2
CLR
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6
VOUT 7
VOUT 8
VOUT 9
VOUT 10
VOUT 3903165-prT
Figure 1.
AD5379—. Patent No. 5,969,657; other patents pending.
TABLE OF CONTENTS General Description..........................................................................3
Specifications......................................................................................4
AC Characteristics........................................................................5
Timing Characteristics......................................................................6
Serial Interface..............................................................................6
Parallel Interface...........................................................................9
Absolute Maximum Ratings...........................................................11
ESD Caution................................................................................11
Pin Configuration and Function Descriptions............................12
Terminology.....................................................................................15
Typical Performance Characteristics............................................16
Functional Description...................................................................18
DAC Architecture—General.....................................................18
Channel Groups..........................................................................18
Transfer Function.......................................................................18
VBIAS Function.............................................................................19
Reference Selection....................................................................19
Calibration...................................................................................20
Clear Function............................................................................20
BUSY and LDAC Functions......................................................20
FIFO Vs. NoN-FIFO Operation...............................................21
BUSY Input Function................................................................21
Power-On Reset Function.........................................................21
RESET Input Function..............................................................21
Increment/Decrement Function..............................................21
Interfaces...........................................................................................22
Parallel Interface.........................................................................22
Serial Interface............................................................................22
Data Decoding.................................................................................24
Address Decoding...........................................................................25
Power Supply Decoupling..............................................................26
Typical Application Circuit............................................................27
Outline Dimensions........................................................................28
Ordering Guide..........................................................................28
REVISION HISTORY Revision 0: Initial Version
GENERAL DESCRIPTION The AD5379 contains 40, 14-bit DACs in one CSPBGA package.
The AD5379 provides a bipolar output range determined by the
voltages applied to the VREF(+) and VREF(−) inputs. The
maximum output voltage span is 17.5 V, corresponding to a
bipolar output range of −8.75 V to +8.75 V, and is achieved with
reference voltages of VREF(−) = −3.5 V and VREF(+) = +5 V.
The AD5379 offers guaranteed operation over a wide VSS/VDD
supply range from ±11.4 V to ±16.5 V. The output amplifier
headroom requirement is 2.5 V operating with a load current of
1.5 mA and 2 V operating with a load current of 0.5 mA.
The AD5379 contains a double-buffered parallel interface in
which 14 data bits are loaded into one of the input registers
under the control of the WR, CS, and DAC channel address
pins, A0 to A7. It also has a 3-wire serial interface, which is
compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface
standards and can handle clock speeds of up to 50 MHz.
The DAC outputs are updated on reception of new data into the
DAC registers. All the outputs can be updated simultaneously
by taking the LDAC input low. Each channel has a program-
mable gain and an offset adjust register.
Each DAC output is gained and buffered on-chip with respect
to an external REFGND input. The DAC outputs can also be
switched to REFGND via the CLR pin.
Table 1. High Channel Count, Low Voltage Single-Supply DACs SPECIFICATIONS VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = 5 V; VREF(−) = −3.5 V; AGND = DGND = REFGND = 0 V;
VBIAS = 5 V; CL = 200 pF to GND; RL = 11 kΩ to 3 V; gain = 1; offset = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. Temperature range for A Version: −40°C to +85°C. Typical specifications are at 25°C.
2 Guaranteed by design and characterization, not production tested. Where θJ represents the package thermal impedance.
AC CHARACTERISTICS VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = 5 V; VREF(−) = −3.5 V; AGND = DGND = REFGND = 0 V;
VBIAS = 5 V; CL = 220 pF; RL = 11 kΩ to 3 V; gain = 1; offset = 0 V.
Table 3. Guaranteed by design and characterization, not production tested.
TIMING CHARACTERISTICS
SERIAL INTERFACE VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = 5 V; VREF(−) = −3.5 V; AGND = DGND = REFGND = 0 V;
VBIAS = 5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V. See Figure 4 and Figure 5.
4 Standalone mode only. This is measured with the load circuit of Figure 2.
6 This is measured with the load circuit of Figure 3. Daisy-chain mode only.
OUTPUT
PIN
VCC
VOL2.2kΩ03165-prT
Figure 2. Load Circuit for BUSY Timing Diagram
200µA
200µA
IOL
IOH
OUTPUT
PIN03165-prT
Figure 3. Load Circuit for SDO Timing Diagram
BUSY
LDAC1
VOUT1
DIN
SCLK
LDAC2
VOUT2
CLR
VOUT
1LDAC ACTIVE DURING BUSY
2LDAC ACTIVE AFTER BUSY
RESET
VOUT
BUSY
SYNC03165-prT
Figure 4. Serial Interface Timing Diagram (Standalone Mode)
03165-prT
SCLK
SYNC
DIN
SDO
LDAC
BUSY
Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)
PARALLEL INTERFACE VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; AGND = DGND = DUTGND = 0 V; VREF(+) = 5 V;
VREF(−) = −3.5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 5. 1 Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
3 See Figure 6. Measured with load circuit in Figure 2.
REG0,
REG1,
A7–A02
DB12–DB0
BUSY
LDAC1
VOUT1
LDAC2
VOUT2
CLR
VOUT
RESET
VOUT
BUSY03165-prT
Figure 6. Parallel Interface Timing Diagram
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 6. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or
any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 234567891011123456789101112
AD5379
TOP VIEW03165-prT
Figure 7. Pin Configuration
Table 7. 108-Lead CSPBGA Ball Configuration
CSPBGA
Number Ball Name A1 REG0
A2 VCC3
A3 DB10
A4 AGND4
A5 VBIAS
A6 VOUT5
A7 AGND3
A8 REFGNDA1
A9 VDD5
A10 VSS5
A11 VSS4
A12 VDD4
B1 REG1
B2 DGND4
B3 DB9
B4 CLR
B5 VOUT7
B6 VOUT6
B7 VOUT0
B8 VOUT1
B9 VOUT2
B10 VOUT31
B11 REFGNDD1
B12 VOUT30
C1 DB13
C2 DB12/SCLK
C3 DB11/DIN
CSPBGA
Number Ball Name C4 SER/PAR1
C5 LDAC
C6 VOUT8
C7 VOUT3
C8 VOUT4
C9 VOUT9
C10 VOUT34
C11 VOUT32
C12 VOUT33
D1 DB7
D2 DB8
D3 DGND1
D10 VREF1(−)
D11 VOUT35
D12 VOUT36
E1 DB5
E2 DB6
E3 VCC1
E10 REFGNDB2
E11 VOUT37
E12 VOUT38
F1 DB4
F2 DB3
F3 DB2
F10 VDD3
F11 REFGNDD2
F12 VOUT39
CSPBGA
Number Ball Name G1 DB1
G2 DB0
G3 BUSY
G10 VSS3
G11 VOUT29
G12 REFGNDC2
H1 WR/DCEN
H2 SDO3
H3 CS/SYNC
H10 VOUT28
H11 VOUT26
H12 VOUT27
J1 A0
J2 A1
J3 A2
J10 VOUT19
J11 VOUT24
J12 VOUT25
K1 A4
K2 A5
K3 A3
K4 DGND2
K5 REFGNDA2
K6 VREF2(−)
K7 VOUT12
K8 VOUT13
K9 VOUT16
CSPBGA
Number Ball Name K10 VOUT18
K11 VOUT22
K12 VOUT23
L1 A7
L2 A6
L3 N/C2
L4 RESET3
L5 VOUT17
L6 AGND2
L7 VOUT14
L8 VOUT10
L9 VDD1
L10 VREF2(+)
L11 VOUT20
L12 VOUT21
M1 DGND3
M2 VCC2
M3 FIFOEN1
M4 AGND1
M5 VOUT15
M6 VOUT11
M7 REFGNDB1
M8 VREF1(+)
M9 VSS1
M10 VSS2
M11 VDD2
M12 REFGNDC1
1 Internal 1 MΩ pull-down device on this logic input. Therefore, it can be left floating and defaults to a logic low condition. N/C—Do not connect to this pin. Internal active pull-up device on these logic inputs. They default to a logic high condition. Internal 1 MΩ pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.
Table 8. Pin Function Descriptions
These serial interface signals do not require separate pins, but share parallel interface pins.
