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AD53513JSQ
Quad Ultrahigh-Speed Pin Driver with High-Z and VTERM Modes
REV.0
Quad Ultrahigh-Speed Pin Driver
with High-Z and VTERM Modes
FUNCTIONAL BLOCK DIAGRAM
FEATURES
500MHz Driver Operation (1 Gb/s)
Driver Inhibit Function
100 ps Edge Matching
Guaranteed Industry Specifications� Output Impedance
5 V/ns Slew Rate
Variable Output Voltages for ECL, TTL, and CMOS
High-Speed Differential Inputs for Maximum Flexibility
Ultrasmall 100-Lead LQFP Package with Built-In
Heat Sink
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation and Characterization Equipment
PRODUCT DESCRIPTIONThe AD53513 is a quad high-speed pin driver designed for use
in digital or mixed-signal test systems. Combining a high-speed
monolithic process with a convenient surface-mount package,
this product attains superb electrical performance while preserving
optimum packaging densities and long-term reliability in a
100-lead, LQFP package with built-in heat sink.
Featuring unity gain programmable output levels of –2.5V to
+5.5V, with output swing capability of less than 200 mV toV, the AD53513 is designed to stimulate ECL, TTL, and
CMOS logic families, as well as high-speed memory. The
1.0Gb/s data rate capacity and matched output impedance
allow for real-time stimulation of these digital logic families.
To test I/O devices, the pin driver can be switched into a high
impedance state (Inhibit Mode), electrically removing the driver
from the path. The pin driver leakage current in inhibit is typically
100 nA and output charge transfer entering inhibit is typically less
than 20 pC.
The AD53513 transition from HI/LO or to inhibit is controlled
through the data and inhibit inputs. The input circuitry uses
high-speed differential inputs with a common-mode range ofV. This allows for direct interface to precision differential
ECL timing. The analog logic HI/LO inputs are equally easy
to interface. Typically requiring 10 µA of bias current, the
AD53513 can be directly coupled to the output of a digital-
to-analog converter.
Each channel of the AD53513 has a Mode Select Pin RLD,
which is a single-sided logic input. The logic threshold is set by
the VBB input which is common to all four channels. The RLD
Mode Select controls whether inhibit puts the driver in High-Z
or VTERM mode. (Refer to Table I.) All of the digital logic inputs
(DATA, DATAB, INH, INHB, RLD, VBB), must share a
common set of logic levels. The VBB threshold should be set to
the midrange of the logic levels. For example, if ECL levels of
–0.8 V to –1.8 V are used, VBB should be set to –1.3 V.
The AD53513 is available in a 100-lead, LQFP package with a
built-in heat sink and is specified to operate over the ambient
commercial temperature range of –25°C to +85°C.
AD53513–SPECIFICATIONS
(All specifications are at TJ = 85�C � 5�C, +VS = +9V � 3%, –VS = –6V � 3% unless otherwise noted. All temperature coefficients are measured
at TJ = 75�C–95�C). (A 39 nF capacitor must be connected between VCC and VHDCPL and between VEE and VLDCPL.)
AD53513
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53513 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1Power Supply Voltage
+VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
–VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7V
+VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Inputs
DATA, DATA, INH, INH, RLD, VBB . . . . . . . +5V, –3V
DATA to DATA, INH to INH, RLD, VBB . . . . . . . . . ±3V
VH, VL, VT to GND . . . . . . . . . . . . . . . . . . . . . . +7V, –2V
VH to VL(VH – VT) and (VT – VL) . . . . . . . . . . . . . . . . ±9V
Outputs
VOUT Short Circuit Duration . . . . . . . . . . . . . . . Indefinite2
VOUT Range in Inhibit Mode
VHDCPL . . . . . Do Not Connect Except for Capacitor to VCC
VLDCPL . . . . . Do Not Connect Except for Capacitor to VEE
THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V, 0V
Environmental
Operating Temperature (Junction) . . . . . . . . . . . . . . . 175°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec)3 . . . . . . . . . . . 260°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2Output short circuit protection is guaranteed as long as proper heat sinking is
employed to ensure compliance with the operating temperature limits.
3To ensure lead coplanarity (±0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in environments at 24°C
±5°C (75°F ±10°F) with relative humidity not to exceed 65%.
ORDERING GUIDENOTES
Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device.
*Typical parameters are not production tested but guaranteed through characterization.
Specifications subject to change without notice.
C01540–0–1/02(0)
PRINTED IN U.S.A.
AD53513
PIN CONFIGURATION
VT1VT2VHDCPL1VCCVCCTVCCTHERMPWRGNDVH1PWRGNDPWRGNDVL1PWRGNDVCCVCCPWRGNDVH2PWRGNDPWRGNDVL2PWRGNDVEEVEERLD1RLD2
VBB
VT4VT3
VHDCPL4
VCCVCC
PWRGND
VH4
PWRGNDPWRGND
VL4
PWRGND
VCCVCC
PWRGND
VH3
PWRGNDPWRGND
VL3
PWRGND
VEEVEE
RLD4RLD3
GND
DATA1
DATAB1
INH1
INB1
PWRGND
INHB2
INH2
VEE
VEE
DATAB2
DATA2
PWRGND
DATA3
DATAB3
VEE
VEE
INH3
INHB3
PWRGND
INHB4
INH4
DATAB4
DATA4
GND
HQGND1
HQGND1
OUT1
HQGND1
VLDCPL1
PWRGND
VHDCPL2
HQGND2
OUT2
HQGND2
HQGND2
VLDCPL2
PWRGND
VLDCPL3
HQGND3
HQGND3
OUT3
HQGND3
VHDCPL3
PWRGND
VLDCPL4
HQGND4
OUT4
HQGND4
HQGND4
NC = NO CONNECT
NOTE THAT THE DIE IS MOUNTED TO THE BACK OF THE HEAT SLUG.
THE PACKAGE IS MOUNTED TO THE BOARD HEAT SLUG UP.
OUTLINE DIMENSIONSDimensions shown in inches and (mm).
100-Lead LQFP_ED Package
(SQ-100)
Table I.Driver Truth Table
:
www.ic-phoenix.com
.
