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AD53500JRP
High Speed, High Current Capability Pin Driver
REV.0
High Speed, High Current
Capability Pin Driver
FUNCTIONAL BLOCK DIAGRAM
FEATURES
–2 V to +6 V Output Range
2.5 V Output Resistance
2.5 ns Tr/Tf for a 3 V Step
300 MHz Toggle Rate
Can Drive 25 V Lines and Lower
Peak Dynamic Current Capability of 400 mA
Inhibit Leakage <1 mA
On-Chip Temperature Sensor
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation and Characterization Equipment
PRODUCT DESCRIPTION:The AD53500 is a complete high speed driver designed for use
in digital or mixed signal test systems where high speed and high
output drive capabilities are needed. Combining a high speed
monolithic process and a unique surface mount package, this
product attains superb electrical performance while preserving
optimum packing densities and long-term reliability thanks to an
ultrasmall 20-lead, PSOP package with built-in heat sink.
High and low reference levels can be set within a –2 V to +6 V
range with low offset voltage and high gain accuracy. A 2.5 W
output resistance allows use of an external backmatch resistor for
application to 50 W, 25 W or other complex impedance load
requirements. Without a backmatch resistor it is also capable of
driving highly capacitive loads, typically achieving a rise/fall time
of less than 10 ns with a 1000 pF capacitance. To test I/O
devices, the pin driver can be switched into a high impedance
state (Inhibit Mode), electrically removing the driver from the
path. The pin driver leakage current in inhibit is typically less
than 1 mA and output capacitance is typically less than 18 pF.
Transitions from HI/LO or to inhibit are controlled through the
data and inhibit inputs. The input circuitry utilizes high-speed
differential inputs with a common-mode range of –2 V to +5 V.
This allows for direct interface to the precision of differential
ECL timing or the simplicity of stimulating the pin driver from a
single-ended CMOS or TTL logic source or any combination
over the common-mode range. The analog logic HI/LO inputs
are equally easy to interface, typically requiring 50 mA of bias
current.
AD53500–SPECIFICATIONS(All specifications are at TJ = +858C 6 58C, +VS = +10 V 6 3%, –VS = +6 V 6 3%
unless otherwise noted. All temperature coefficients are measured over TJ = 758C–958C). (In test figures, voltmeter loading is 1 MV or greater,
scope probe loading is 100 kV in parallel with 5 pF.) 39 nF capacitors must be connected between VCC and VHDCPL and between VEE and VLDCPL.REFERENCE INPUTS
DYNAMIC PERFORMANCE, DRIVE
AD53500
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
NOTES
Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1Power Supply Voltage
+VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+11 V
–VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–7 V
+VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18 V
Inputs
DATA, DATA, INH, INH . . . . . . . . . . . . . . . .+5 V, –3 V
DATA to DATA, INH to INH . . . . . . . . . . . . . . . .–3 V
VH, VL to GND . . . . . . . . . . . . . . . . . . . . . . . . .+7 V, –3 V
VH to VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+10 V, 0 V
Outputs
VOUT Short Circuit Duration to Ground . . . . . . .Indefinite2
VOUT Range in Inhibit Mode . . . . . . . . . . . . . See Figure 1
VHDCPL . . . . . . . . Do Not Connect Except for Cap to VCC3
VLDCPL . . . . . . . . . Do Not Connect Except for Cap to VEE3
THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+VS, 0 V
Environmental
Operating Temperature (Junction) . . . . . . . . . . . . . .+175°C
Storage Temperature . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec)4 . . . . . . . . . .+260°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.Output short circuit protection is guaranteed as long as proper heat sinking is
employed to ensure compliance with the operating temperature limits.The VHDCPL and VLDCPL capacitors may be replaced by a low value resistor for higher
dc-current drive capability.To ensure lead coplanarity (–0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in environments at 24°C 5°C (75°F – 10°F) with relative humidity not to exceed 65%.
VH, VL
VOUT
VOUT = (MIN) = –3V
FIGURE 1 SHOWS THE MAXIMUM ALLOWABLE LIMITS FOR VOUT AS A FUNCTION
OF VHIGH AND VLOW WHEN THE DRIVER IS OPERATING IN INHIBIT MODE. THE
LIMITS, AS STATED BEFORE, ARE MAXIMUM RATINGS ONLY, AND SHOULD NOT
BE USED AS THE PART'S NORMAL OPERATING RANGE. THIS RANGE APPLIES
ONLY TO SUPPLIES OF +VS = +10V AND –VS = –6V AND SHOULD BE DERATED
PROPORTIONALLY FOR LOWER SUPPLIES.
VHIGH / VLOWFigure 1.Absolute Maximum Ratings for VOUT
AD53500
PIN CONFIGURATION
VCCTHERM
VCCTVCC
VHDCPLVH
GNDGND
VOUTGND
GNDVL
VLDCPLGND
VEEDATA
VEEDATA
INHINH
Table I.Pin Driver Truth Table
Table II.Package Thermal Characteristics
PIN FUNCTION DESCRIPTIONSVOUT
ORDERING GUIDE
capacitor to the positive supply (and the VLDCPL capacitor to the
negative supply)—failure to do so causes considerable thermal
stress in the current-limiting resistor(s) during normal supply
sequencing and may ultimately cause them to fail, rendering the
part nonfunctional. Finally, the AD53500 may appear to func-
tion normally for small output steps (less than 3 V or so) if one
or both of these caps is absent, but it may exhibit excessive rise
or fall times for steps of larger amplitude.
The AD53500 does not require special power-supply sequenc-
ing. However, good design practice dictates that digital and
analog control signals not be applied to the part before the sup-
plies are stable. Violating this guideline will not normally de-
stroy the part, but the active inputs can draw considerable
current until the main supplies are applied.
Figure 2.Simplified Schematic of the AD53500 Output
Stage and Positive Current-Limit Circuitry
APPLICATION INFORMATION
Power Supply Distribution, Bypassing and SequencingThe AD53500 draws substantial transient currents from its
power supplies when switching between states and careful de-
sign of the power distribution and bypassing is key to obtaining
specified performance. Supplies should be distributed using
broad, low inductance traces or (preferably) planes in a multi-
layered board with a dedicated ground-plane layer. All of the
device’s power supply pins should be used to minimize the inter-
nal inductance presented by the part’s bond wires. Each supply
must be bypassed to ground with at least one 0.1 mF capacitor;
chip-style capacitors are preferable as they minimize inductance.
One or more 10 mF (or greater) Tantalum capacitors per board
are also advisable to provide additional local energy storage.
The AD53500’s current-limit circuitry also requires external
bypass capacitors. Figure 2 shows a simplified schematic of the
positive current-limit circuit. Excessive collector current in
output transistor Q49 creates a voltage drop across the 5 W
resistor, which turns on PNP transistor Q48. Q48 diverts the
rising-edge slew current, shutting down the current mirror and
removing the output stage’s base drive. The VHDCPL pin should
be bypassed to the positive supply with a 0.039 mF capacitor,
while the VLDCPL pin (not shown) requires a similar capacitor to
the negative supply. These capacitors ensure that the AD53500
does not current-limit during normal output transitions up its
full 8 V rated step size. Both capacitors must have minimum-
length connections to the AD53500. Here again, chip capacitors
are ideal.
Several points about the current-limit circuitry should be noted.
First, the limiting currents are not tightly controlled, as they are
functions of both absolute transistor VBE and junction tempera-
ture; higher dc output current is available at lower junction
temperatures. Second, it is essential to connect the VHDCPL
AD535000.1
C170.039
C160.039
OUT
SMA
DATA
–2V
SMA
INH
–2V
NOTES:1. 50
TERMINATION TO BE AS CLOSE TO RECEIVER AS POSSIBLE.
(END OF TRACE MARKED BY *). THROUGH SMA CONNECTS BETWEEN MC10EL16 OUTPUTS AND DUT.2. NO VIAS ALLOWED ON V
OUT
LINE.
3. SMA ON V
OUT
TO BE MOUNTED ON ITS SIDE FOR BEST IMPEDANCE
MATCH.4. ONE DIMENSION OF BOARD TO BE 4 1/2 INCHES.5. DUT PACKAGE IS TO BE CENTERED ON BOARD.6. ALL RESISTORS AND NONELECTROLYTIC CAPS ARE 0805-SIZE SURFACE MOUNT.7. SEE DATA FOR HIDDEN POWER AND GROUND PINS ON LOGIC GATES.8. ALL 100nF BYPASS CAPACITORS TO BE LOCATED CLOSE TO PACKAGE.9. PCB IS TO BE FOUR-LAYER WITH POWER GND ( ) AND –2V AS INNER PLANES.
GND
C110.1
–5.2VDB15
JP1
–2VV
THERM–5.2V+V
