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AD5348BRU
2.5 V to 5.5 V, Parallel Interface 2.5 V to 5.5 V, Parallel Interface
2.5 V to 5.5 V, Parallel Interface
Octal Voltage Output 8-/10-/12-Bit DACs
Rev. 0
FEATURES
AD5346: octal 8-bit DAC
AD5347: octal 10-bit DAC
AD5348: octal 12-bit DAC
Low power operation: 1.4 mA (max) @ 3.6 V
Power-down to 120 nA @ 3 V, 400 nA @ 5 V
Guaranteed monotonic by design over all codes
Rail-to-rail output range: 0 V to VREF or 0 V to 2 × VREF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
Readback
Buffered/unbuffered reference inputs
20 ns WR time
38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging
Temperature range: –40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit
DACs, operating from a 2.5 V to 5.5 V supply. These devices
incorporate an on-chip output buffer that can drive the output
to both supply rails, and also allow a choice of buffered or
unbuffered reference input.
The AD5346/AD5347/AD5348 have a parallel interface. CS
selects the device and data is loaded into the input registers on
the rising edge of WR. A readback feature allows the internal
DAC registers to be read back through the digital port.
The GAIN pin on these devices allows the output range to be
set at 0 V to VREF or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultane-
ous update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
All three parts are pin compatible, which allows users to select
the amount of resolution appropriate for their application
without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
DGND
VOUTB
VOUTC
VOUTD
VOUTE
VOUTG
VOUTH
VOUTF
VDD
VOUTA
VREFEF
VREFAB
GAIN
DB11
DB0
CLR
LDAC.
BUF
VREFGH
VREFCDAGND001Figure 1. . Patent No. 5,969,657; other patents pending.
TABLE OF CONTENTS Specifications.....................................................................................3
AC Characteristics............................................................................4
Timing Characteristics.....................................................................5
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
AD5346 Pin Configurations and Function Descriptions...........7
AD5347 Pin Configurations and Function Descriptions...........8
AD5348 Pin Configurations and Function Descriptions...........9
Terminology....................................................................................10
Typical Performance Characteristics...........................................12
Functional Description..................................................................16
Digital-to-Analog Section.........................................................16
Resistor String.............................................................................16
DAC Reference Input.................................................................16
Output Amplifier........................................................................16
Parallel Interface.........................................................................17
Power-On Reset..........................................................................17
Power-Down Mode....................................................................17
Suggested Data Bus Formats.....................................................18
Applications Information..............................................................19
Typical Application Circuits.....................................................19
Driving VDD from the Reference Voltage.................................19
Bipolar Operation Using the AD5346/AD5347/AD5348.....19
Decoding Multiple AD5346/AD5347/AD5348s....................20
AD5346/AD5347/AD5348 as Digitally Programmable
Window Detectors......................................................................20
Programmable Current Source................................................20
Coarse and Fine Adjustment Using the
AD5346/AD5347/AD5348.......................................................21
Power Supply Bypassing and Grounding................................21
Outline Dimensions.......................................................................23
Ordering Guides.........................................................................24
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS
Table 1. VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX,
unless otherwise noted
See footnotes after the AC Characteristics table.
AC CHARACTERISTICS6
Table 2. VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. See Terminology section. Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095). DC specifications tested with outputs unloaded. This corresponds to x codes. x = deadband voltage/LSB size. Guaranteed by design and characterization, not production tested. For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and
the offset plus gain error must be positive.
TO OUTPUT
PINVOH(min) + VOL(max)CL
50pF
200µA
200µA03331-0-002 Figure 2. Load Circuit for Digital Output Timing Specifications
TIMING CHARACTERISTICS1, 2, 3
Table 3. VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
DATA,
GAIN, BUF
LDAC1
LDAC2
CLR
NOTES1. SYNCHRONOUS LDAC UPDATE MODE
A0–A2
A0–A2
DATA
ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25°C, unless otherwise noted Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5346 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
LDAC
AGND
VOUTD
VREFCD
VREFEF
VREFGH
VOUTC
VOUTB
VOUTA
VREFAB
VDD
VOUTH
VOUTG
VOUTF
VOUTE
DGND
BUF03331-0-005
Figure 5. AD5346 Pin Configuration—TSSOP
LDACA0
AGND
VOUTD
VOUTC
VOUTB
VOUTAV
DB0
DB1
DB2
CLRGAIN
DB7
DB6
DB3
DB4
DB5
VOUTH
VOUTG
VOUTF
VOUTE
DGND
BUF
AGND
DGNDDGNDDGNDDGND03331-0-006
Figure 6. AD5346 Pin Configuration—LFCSP
Table 5. AD5346 Pin Function Descriptions
AD5347 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
LDAC
AGND
VOUTD
VREFCD
VREFEF
VREFGH
VOUTC
VOUTB
VOUTA
VREFAB
VDD
VOUTH
VOUTG
VOUTF
VOUTE
DGND
BUF03331-0-007
Figure 7. AD5347 Pin Configuration—TSSOP
LDACA0
AGND
VOUTD
VOUTC
VOUTB
VOUTAV
DB2
DB3
DB4
CLRGAIN
DB9
DB8
DB5
DB6
DB7
VOUTH
VOUTG
VOUTF
VOUTE
DGND
BUF
AGND
DGNDDGND03331-0-008
Figure 8. AD5347 Pin Configuration—LFCSP
Table 6. AD5347 Pin Function Descriptions
AD5348 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
LDAC
AGND
VOUTD
VREFCD
VREFEF
VOUTC
VOUTB
VOUTA
VREFAB
VDD
VOUTH
VOUTG
VOUTF
VOUTE
DGND
BUF03331-0-009
Figure 9. AD5348 Pin Configuration—TSSOP
LDACA0
AGND
VOUTD
VOUTC
VOUTB
VOUTAV
DB4
DB5
DB6
CLRGAIN
DB11
DB10
DB7
DB8
DB9
VOUTH
VOUTG
VOUTF
VOUTE
DGND
BUF
AGND03331-0-010
Figure 10. AD5348 Pin Configuration—LFCSP
Table 7. AD5348 Pin Function Descriptions TERMINOLOGY
Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL versus code plots can be seen in Figure 14,
Figure 15, and Figure 16.
Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ± 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Typical DNL versus code plots can be
seen in Figure 17, Figure 18, and Figure 19.
Gain Error This is a measure of the span error of the DAC, including any
error in the gain of the buffer amplifier. It is the deviation in
slope of the actual DAC transfer characteristic from the ideal
and is expressed as a percentage of the full-scale range. This is
illustrated in Figure 11.
Offset Error This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
If the offset voltage is positive, the output voltage still positive at
zero input code. This is shown in Figure 12. Because the DACs
operate from a single supply, a negative offset cannot appear at
the output of the buffer amplifier. Instead, there is a code close
to zero at which the amplifier output saturates (amplifier
footroom). Below this code there is a dead band over which the
output voltage does not change. This is illustrated in Figure 13.
OUTPUT
VOLTAGE
DAC CODE03331-0-011
Figure 11. Gain Error
OUTPUTVOLTAGE
DAC CODE
POSITIVE
OFFSET03331-0-012
Figure 12. Positive Offset Error and Gain Error
AMPLIFIER
FOOTROOM
(~1mV)
NEGATIVE
OFFSET
OUTPUT
VOLTAGE
NEGATIVE
OFFSET03331-0-013
Figure 13. Negative Offset Error and Gain Error
Offset Error Drift This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error Drift This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
DC Power-Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V and VDD is varied ±10%.
DC Crosstalk This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in µV.
Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being
updated, i.e., LDAC is high. It is expressed in dB.
Channel-to-Channel Isolation This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference inputs of the other DACs.
It is measured by grounding one VREF pin and applying a 10 kHz,
4 V p-p sine wave to the other VREF pins. It is expressed in dB.
Major-Code Transition Glitch Energy This is the energy of the impulse injected into the analog output
when the DAC changes state. It is normally specified as the area
of the glitch in nV-s and is measured when the digital code is
changed by 1 LSB at the major carry transition (011 . . . 11 to
100 . . . 00 or 100 . . . 00 to 011 . . . 11).
Digital Feedthrough This is a measure of the impulse injected into the analog output
of the DAC from the digital input pins of the device, but it is
measured when the DAC is not being written to, CS held high.
It is specified in nV-s and is measured with a full-scale change
on the digital input pins, i.e., from all 0s to all 1s and vice versa.
Digital Crosstalk This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV-s.
Analog Crosstalk This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.
DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the LDAC pin set
low and monitoring the output of another DAC. The energy of
the glitch is expressed in nV-s.
Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measure of the
harmonics present on the DAC output. It is measured in dB.
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
INL E
RROR (LS
–0.5Figure 14. AD5346 Typical INL Plot
CODE
INL E
RROR (LSFigure 15. AD5347 Typical INL Plot
CODE
INL E
RROR (LS
–12Figure 16. AD5348 Typical INL Plot
CODE
DNL E
ROR (LS
0.2Figure 17. AD5346 Typical DNL Plot
CODE
DNL E
RROR (LS
–0.2Figure 18. AD5347 Typical DNL Plot
CODE
DNL E
RROR (LS
–0.5Figure 19. AD5348 Typical DNL Plot
