AD5337ARMZ-REEL7 ,2.5 V to 5.5 V, 250 µA, 2-Wire Interface Dual Voltage Output, 8-Bit D/A Converterspecifications TMIN to TMAX, unless otherwise noted. Table 1. Grade A Grade B 1 2Parameter Min ..
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AD5340BRU ,2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACsGENERAL DESCRIPTIONAD5330: Single 8-Bit DAC in 20-Lead TSSOPThe AD5330/AD5331/AD5340/AD5341 are sin ..
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AD9248BCPZ-40 ,Dual 14-Bit, 20/40/65 MSPS, 3 V ADCfeatures dual high performance sample-and performance to suit an application. hold amplifiers and a ..
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AD9248BST-40 ,14-Bit/ 20/40/65 MSPS Dual A/ D Converterfeatures dual high performance sample-and performance to suit an application. hold amplifiers and a ..
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AD5337ARM-AD5337ARM-REEL7-AD5337ARMZ-REEL7-AD5337BRMZ-AD5338BRM
2.5 V to 5.5 V, 250 µA, 2-Wire Interface Dual Voltage Output, 8-Bit D/A Converter
2.5 V to 5.5 V, 250 µA, 2-Wire Interface
Dual-Voltage Output, 8-/10-/12-Bit DACs
Rev. A
FEATURES
AD5337
2 buffered 8-bit DACs in 8-lead MSOP
AD5338, AD5338-1
2 buffered 10-bit DACs in 8-lead MSOP
AD5339
2 buffered 12-bit DACs in 8-lead MSOP
Low power operation: 250 mA @ 3 V, 300 mA @ 5 V
2-wire (I2C®compatible) serial interface
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
3 power-down modes
Double-buffered input logic
Output range: 0 V to VREF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC function)
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit buffered
voltage output DACs in an 8-lead MSOP package, which
operate from a single 2.5 V to 5.5 V supply, consuming 250 µA
at 3 V. On-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/µs. A 2-wire serial interface operates at
clock rates up to 400 kHz. This interface is SMBus-compatible
at VDD < 3.6 V. Multiple devices can be placed on the same bus.
The references for the two DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on reset circuit that ensures that the DAC outputs power
up to 0 V and remain there until a valid write to the device
takes place. A software clear function resets all input and DAC
registers to 0 V. A power-down feature reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated
equipment. The power consumption is typically 1.5 mW at 5 V
and 0.75 mW at 3 V, reducing to 1 µW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
SCLVOUTA
VDDREFINVOUTBA0
SDA
GND03756-A
Figure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
AC Characteristics........................................................................5
Timing Characteristics................................................................6
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Terminology......................................................................................9
Typical Performance Characteristics...........................................11
Functional Description..................................................................15
Digital-to-Analog Converter Section......................................15
Resistor String.............................................................................15
DAC Reference Inputs...............................................................15
Output Amplifier........................................................................15
Power-on Reset...........................................................................15
Serial Interface............................................................................15
Write Operation..........................................................................17
Read Operation...........................................................................18
Double-Buffered Interface........................................................19
Power-Down Modes..................................................................19
Applications.....................................................................................20
Typical Application Circuit.......................................................20
Bipolar Operation.......................................................................20
Multiple Devices on One Bus...................................................20
Product as a Digitally Programmable Window Detector.....21
Coarse and Fine Adjustment Capabilities...............................21
Power Supply Decoupling.........................................................21
Outline Dimensions.......................................................................24
Ordering Guide..........................................................................24
REVISION HISTORY
10/04—Changed Data Sheet from Rev. 0 to Rev. A Updated Format..................................................................Universal
Added AD5338-1................................................................Universal
Changes to Specifications................................................................4
Updated Outline Dimensions.......................................................24
Changes to Ordering Guide..........................................................24
11/03—Rev. 0: Initial Version
SPECIFICATIONS VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
For explanations of the specific parameters, see the Termin section. ology
2 Temperature range: (A and B versions): −40°C to +105°C; typical at 25°C. DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5337 (Codes 8 to 248); AD5338, AD5338-1 (Codes 28 to 995); AD5339 (Codes 115 to 3981). Guaranteed by design and characterization; not production tested.
6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be
positive.
7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
AC CHARACTERISTICS1VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. 1 Guaranteed by design and characterization; not production tested. Temperature range: A and B versions: −40°C to +105°C; typical at 25°C.
3 For explanations of the specific parameters, see the Termin section. ology
TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3. 1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
2 CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 VDD and 0.7 VDD.
STOP
START
CONDITION
REPEATED
STARTCONDITIONCONDITION03756-A
Figure 2. 2-Wire Serial Interface Timing Diagram
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 4. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD
VOUTA
VOUTB
REFIN03756-A
Figure 3. Pin Configuration
Table 5. Pin Function DescriptionsTERMINOLOGY
Relative Accuracy (Integral Nonlinearity, INL) For the DAC, relative accuracy, or integral nonlinearity (INL),
is a measure, in LSBs, of the maximum deviation from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL vs. code plots can be seen in Figure 6, Figure 7, and
Figure 8.
Differential Nonlinearity (DNL) The difference between the measured change and the ideal 1 LSB
change between any two adjacent codes. A specified differential
nonlinearity of ±1 LSB maximum ensures monotonicity. This
DAC is guaranteed monotonic by design. Typical DNL vs. code
plots can be seen in Figure 9, Figure 10, and Figure 11.
Offset Error A measure of the offset error of the DAC and the output
amplifier, expressed as a percentage of the full-scale range.
Gain Error A measure of the span error of the DAC. It is the deviation in
slope of the actual DAC transfer characteristic from the ideal,
expressed as a percentage of the full-scale range.
Offset Error Drift A measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error Drift A measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V and VDD is varied ±10%.
DC Crosstalk The dc change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in µV.
Reference Feedthrough The ratio of the amplitude of the signal at the DAC output to
the reference input when the DAC output is not being updated.
It is expressed in dB.
Major-Code Transition Glitch Energy The energy of the impulse injected into the analog output when
the code in the DAC register changes state. Normally specified
as the area of the glitch in nV-s and is measured when the
digital code is changed by 1 LSB at the major carry transition
(011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11).
Digital Feedthrough A measure of the impulse injected into the analog output of the
DAC from the digital input pins of the device when the DAC
output is not being updated. Specified in nV-s and measured
with a worst-case change on the digital input pins, such as
changing from all 0s to all 1s or vice-versa.
Digital Crosstalk The glitch impulse transferred to the output of one DAC at mid-
scale in response to a full-scale code change (all 0s to all 1s, or
vice versa) in the input register of another DAC. It is expressed
in nV-s.
DAC-to-DAC Crosstalk The glitch impulse transferred to the output of one DAC due to
a digital code change and subsequent output change of another
DAC. This includes both digital and analog crosstalk. It is
measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s, or vice versa) with the LDAC bit set low
and monitoring the output of another DAC. The energy of the
glitch is expressed in nV-s.
Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output.
Total Harmonic Distortion (THD) The difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measure of the harmonic
distortion present in the DAC output. It is measured in dB.
PLUS
OUTPUTVOLTAGE
NEGATIVEOFFSET
ERROR
AMPLIFIER
FOOTROOM(1mV)
NEGATIVE
OFFSET
ERROR03756-A
Figure 4. Transfer Function with Negative Offset
OUTPUT
VOLTAGE
POSITIVEOFFSET
PLUS03756-A
Figure 5. Transfer Function with Positive Offset
TYPICAL PERFORMANCE CHARACTERISTICS
INL ERROR (LSB)
CODE03756-A
Figure 6. AD5337 Typical INL Plot
03756-A
Figure 7. AD5338 Typical INL Plot
03756-A
DNL ERROR (LSB)50100150200250
CODE03756-A
Figure 9. AD5337 Typical DNL Plot
DNL ERROR (LSB)2004006008001000
CODE03756-A
Figure 10. AD5338 Typical DNL Plot
03756-A
Figure 12. AD5337 INL and DNL Error vs. VREF
Figure 13. AD5337 INL and DNL Error vs. Temperature
Figure 14. AD5337 Offset Error and Gain Error vs. Temperature
Figure 15. Offset Error and Gain Error vs. VDD
Figure 16. VOUT Source and Sink Current Capability
Figure 17. Supply Current vs. Code
