AD5332BRU-AD5333BRU-AD5342BRU Fast Delivery |IC PHOENIX CO.,LIMITED

AD5342BRU ,2.5 V to 5.5 V, 230uA, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACsSPECIFICATIONS(V = 2.5 V to 5.5 V, V = 2 V. R = 2 k to GND; C =200 pF to GND; all speciﬁcations T ..
AD5346BCP ,2.5 V to 5.5 V, Parallel Interface 2.5 V to 5.5 V, Parallel InterfaceAPPLICATIONS contents of the input register and the DAC register to all zeros. Portable battery-pow ..
AD5346BRU ,2.5 V to 5.5 V, Parallel Interface 2.5 V to 5.5 V, Parallel Interfacespecifications TMIN to TMAX, unless otherwise noted 1 B Version 2 Parameter Min Typ Max Unit C ..
AD5348BRU ,2.5 V to 5.5 V, Parallel Interface 2.5 V to 5.5 V, Parallel InterfaceAPPLICATIONS contents of the input register and the DAC register to all zeros. Portable battery-pow ..
AD534JD ,Internally Trimmed Precision IC MultiplierSpecifications shown in boldface are tested on all production units at final electrical1Figures giv ..
AD534JD ,Internally Trimmed Precision IC MultiplierSpecifications subject to change without notic–2– REV. BAD534Model AD534S AD534TMin Typ Max Min Typ ..
AD9251BCPZRL7-65 , 14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
AD9255BCPZRL7-80 , 14-Bit, 125 MSPS/105 MSPS/80 MSPS
AD9260AS ,High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word RateSPECIFICATIONS unless otherwise noted, R = 2 k)BIAS Parameter—Decimation Factor (N) AD9260 (8) AD9 ..
AD9262 ,16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADCfeatures and characteris-PRODUCT HIGHLIGHTS tics unique to the continuous time - architecture sig ..
AD9269 ,16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converterfeatures user-defined test patterns entered via the serial port interface (SPI). a high performance ..
AD9271BSVZ-50 , Octal LNA/VGA/AAF/ADC and Crosspoint Switch

AD5332BRU-AD5333BRU-AD5342BRU
2.5 V to 5.5 V, 230uA, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs
REV.0
2.5V to 5.5V, 230 �A, Parallel Interface
Dual Voltage-Output 8-/10-/12-Bit DACs
AD5332 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
DB7
DB0
CLR
LDAC.
VREFA
VREFB
VOUTA
VOUTB
VDDGND
FEATURES
AD5332: Dual 8-Bit DAC in 20-Lead TSSOP
AD5333: Dual 10-Bit DAC in 24-Lead TSSOP
AD5342: Dual 12-Bit DAC in 28-Lead TSSOP
AD5343: Dual 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 230 �A @ 3V, 300 �A @ 5V
via PD Pin
Power-Down to 80 nA @ 3V, 200 nA @ 5V
2.5V to 5.5V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–VREF or 0–2VREF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Ampliﬁers
Temperature Range: –40�C to +105�C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5332/AD5333/AD5342/AD5343 are dual 8-, 10-, and
12-bit DACs. They operate from a 2.5V to 5.5V supply con-
suming just 230 µA at 3V, and feature a power-down pin, PD
that further reduces the current to 80 nA. These devices incor-
porate an on-chip output buffer that can drive the output to
both supply rails, while the AD5333 and AD5342 allow a choice
of buffered or unbuffered reference input.
The AD5332/AD5333/AD5342/AD5343 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin on the AD5333 and AD5342 allows the output
range to be set at 0V to VREF or 0V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0V and remains there until
valid data is written to the device.
The AD5332/AD5333/AD5342/AD5343 are available in Thin
Shrink Small Outline Packages (TSSOP).
*. Patent Number 5,969,657; other patents pending.
AD5332/AD5333/AD5342/AD5343–SPECIFICATIONS
(VDD = 2.5V to 5.5V, VREF = 2V. RL = 2 k� to GND; CL =200 pF to GND; all speciﬁcations TMIN to TMAX unless otherwise noted.)
OUTPUT CHARACTERISTICS
POWER REQUIREMENTS
NOTESSee Terminology section.Temperature range: B Version: –40°C to +105°C; typical speciﬁcations are at 25°C.Linearity is tested using a reduced code range: AD5332 (Code 8 to 255); AD5333 (Code 28 to 1023); AD5342/AD5343 (Code 115 to 4095).DC speciﬁcations tested with outputs unloaded.This corresponds to x codes. x = Deadband voltage/LSB size.
AD5332/AD5333/AD5342/AD5343
AC CHARACTERISTICS1
Output Voltage Settling Time
Slew Rate
Major Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Speciﬁcations subject to change without notice.
t10
t11
t12
t13
NOTESGuaranteed by design and characterization, not production tested.All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and
timed from a voltage level of (VIL + VIH)/2.See Figure 1.
Speciﬁcations subject to change without notice.
(VDD = 2.5 V to 5.5 V. RL = 2 k� to GND; CL = 200 pF to GND; all speciﬁcations TMIN to TMAX unless
otherwise noted.)
AD5332/AD5333/AD5342/AD5343
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5332/AD5333/AD5342/AD5343 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
VOUT to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . (TJ max – TA)/θJA mW
θJA Thermal Impedance (20-Lead TSSOP) . . . . . 143°C/W
θJA Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W
θJA Thermal Impedance (28-Lead TSSOP) . . . . 97.9°C/W
θJC Thermal Impedance (20-Lead TSSOP) . . . . . . 45°C/W
θJC Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W
θJC Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
AD5332 FUNCTIONAL BLOCK DIAGRAM
DB7
DB0
CLR
LDAC.
VREFA
VREFB
VOUTA
VOUTB
VDDGND
AD5332 PIN FUNCTION DESCRIPTIONS
AD5332 PIN CONFIGURATION
AD5332/AD5333/AD5342/AD5343
AD5333 FUNCTIONAL BLOCK DIAGRAM
DB9
DB0
CLR
LDAC.
VREFA
VREFB
BUF
GAIN
VOUTA
VOUTB
VDDGND
AD5333 PIN FUNCTION DESCRIPTIONS
AD5333 PIN CONFIGURATION
AD5342 FUNCTIONAL BLOCK DIAGRAM
VOUTA
VOUTB
VDD
DB11
DB0
CLR
LDAC.
VREFAGNDVREFB
AD5342 PIN FUNCTION DESCRIPTIONS
AD5342 PIN CONFIGURATION
AD5332/AD5333/AD5342/AD5343
AD5343 FUNCTIONAL BLOCK DIAGRAM..
VOUTA
GND
VOUTB
VDDVREF
HBEN
DB7
DB0
CLR
LDAC
AD5343 PIN FUNCTION DESCRIPTIONS
AD5343 PIN CONFIGURATION
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, Relative Accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL versus Code plot can be seen in Figures
5, 6, and 7.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A speciﬁed differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Typical DNL versus Code plot can be seen in
Figures 8, 9, and 10.
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
ampliﬁer. It is expressed as a percentage of the full-scale range.
If the offset voltage is positive, the output voltage will still be
positive at zero input code. This is shown in Figure 3. Because
the DACs operate from a single supply, a negative offset cannot
appear at the output of the buffer ampliﬁer. Instead, there will
be a code close to zero at which the ampliﬁer output saturates
(ampliﬁer footroom). Below this code there will be a deadband
over which the output voltage will not change.This is illustrated
in Figure 4.
GAIN ERROR
This is a measure of the span error of the DAC (including any
error in the gain of the buffer ampliﬁer). It is the deviation in
slope of the actual DAC transfer characteristic from the ideal
expressed as a percentage of the full-scale range. This is illus-
trated in Figure 2.
DAC CODE
OUTPUT
VOLTAGE
Figure 2.Gain Error
Figure 3.Positive Offset Error and Gain Error
Figure 4.Negative Offset Error and Gain Error
AD5332/AD5333/AD5342/AD5343
OFFSET ERROR DRIFT
This is a measure of the change in Offset Error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
GAIN ERROR DRIFT
This is a measure of the change in Gain Error with changes in tem-
perature. It is expressed in (ppm of full-scale range)/°C.
POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by changes in
the supply voltage. PSRR is the ratio of the change in VOUT to a
change in VDD for full-scale output of the DAC. It is measured
in dBs. VREF is held at 2 V and VDD is varied ±10%.
DC CROSSTALK
This is the dc change in the output level of one DAC at mid-
scale in response to a full-scale code change (all 0s to all 1s and
vice versa) and output change of the other DAC. It is expressed
in µV.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC output
to the reference input when the DAC output is not being updated
(i.e., LDAC is high). It is expressed in dBs.
CHANNEL-TO-CHANNEL ISOLATION
This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of the other DAC. It
is measured by grounding one VREF pin and applying a 10kHz,V peak-to-peak sine wave to the other VREF pin. It is expressed
in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-Code Transition Glitch Energy is the energy of the
impulse injected into the analog output when the DAC changes
state. It is normally speciﬁed as the area of the glitch in nV secs
and is measured when the digital code is changed by 1 LSB at
the major carry transition (011...11 to 100...00 or 100...00
to 011...11).
DIGITAL FEEDTHROUGH
Digital Feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device but is measured when the DAC is not being written to
(CS held high). It is speciﬁed in nV secs and is measured with a
full-scale change on the digital input pins, i.e. from all 0s to all
1s and vice versa.
DIGITAL CROSSTALK
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of the other DAC. It is
expressed in nV-secs.
ANALOG CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of the other DAC. It is measured
by loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-secs.
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
the other DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the LDAC pin set
low and monitoring the output of the other DAC. The energy of
the glitch is expressed in nV-secs.
MULTIPLYING BANDWIDTH
The ampliﬁers within the DAC have a ﬁnite bandwidth. The
Multiplying Bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The Multiplying Bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.

Partno	Mfg	Dc	Qty	Available	Descript
AD5332BRU	AD	N/a	1	avai	2.5 V to 5.5 V, 230uA, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs
AD5333BRU	AD	N/a	2	avai	2.5 V to 5.5 V, 230uA, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs
AD5342BRU	AD	N/a	267	avai	2.5 V to 5.5 V, 230uA, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs