AD5330BRU-AD5331BRU-AD5340BRU Fast Delivery |IC PHOENIX CO.,LIMITED

AD5330BRU ,2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACsSPECIFICATIONS(V = 2.5 V to 5.5 V, V = 2 V. R = 2 k to GND; C = 200 pF to GND; all speciﬁcations T ..
AD5331BRU ,2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACsCHARACTERISTICSunless otherwise noted.)3 B Version2Parameter Min Typ Max Unit Conditions/Co ..
AD5331BRU-REEL7 , 2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
AD5332BRU ,2.5 V to 5.5 V, 230uA, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACsAPPLICATIONS that the DAC output powers on to 0 V and remains there untilPortable Battery-Powered I ..
AD5333BRU ,2.5 V to 5.5 V, 230uA, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACsGENERAL DESCRIPTIONAD5332: Dual 8-Bit DAC in 20-Lead TSSOPThe AD5332/AD5333/AD5342/AD5343 are dual ..
AD5335 ,+2.5V to 5.5V, 500礎 Quad Rail-to-Rail Voltage Output 10-Bit DAC with Parallel Interface in 24-lead TSSOPCHARACTERISTICS4, 7Minimum Output Voltage 0.001 V min Rail-to-Rail Operation4, 7Maximum Output Volt ..
AD9244BST-65 ,14-Bit, 40/65 MSPS Monolithic A/D ConverterSPECIFICATIONS (AVDD = +5 V, CLKVDD=3V, DRVDD = +3.0 V, f = 65 MSPS (-65) or 40MSPS (-40), INPUT RA ..
AD9244BSTZ-40 ,14-Bit 40/65 MSPS IF Sampling Analog-To-Digital ConverterSPECIFICATIONS External Reference, Differential Analog Inputs, unless otherwise noted.)Test AD9 ..
AD9244BSTZ-65 ,14-Bit 40/65 MSPS IF Sampling Analog-To-Digital ConverterGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe AD9244 is a monolithic, single 5 V supply, 14-bit, Low Po ..
AD9245BCP-80 ,14-Bit, 80 MSPS, 3 V A/D Converterapplications in communications, imaging, and to 14 bits and 20 MSPS to 80 MSPS. medical ultrasound. ..
AD9245BCPZ-80 ,14-Bit, 80 MSPS, 3 V A/D Converterapplications in communications, imaging, and to 14 bits and 20 MSPS to 80 MSPS. medical ultrasound. ..
AD9246BCPZ-105 , 14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter

AD5330BRU-AD5331BRU-AD5340BRU
2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
REV.0
2.5 V to 5.5 V, 115 �A, Parallel Interface
Single Voltage-Output 8-/10-/12-Bit DACs
AD5330 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
BUF
GAIN
DB7
DB0.
CLR
LDAC
VREFVDD
VOUTGND
FEATURES
AD5330: Single 8-Bit DAC in 20-Lead TSSOP
AD5331: Single 10-Bit DAC in 20-Lead TSSOP
AD5340: Single 12-Bit DAC in 24-Lead TSSOP
AD5341: Single 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 115 �A @ 3 V, 140 �A @ 5 V
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–VREF or 0–2 VREF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Ampliﬁers
Temperature Range: –40�C to +105�C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5330/AD5331/AD5340/AD5341 are single 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 115 µA at 3 V, and feature a power-down mode that
further reduces the current to 80 nA. These devices incorporate
an on-chip output buffer that can drive the output to both
supply rails, while the AD5330, AD5340, and AD5341 allow a
choice of buffered or unbuffered reference input.
The AD5330/AD5331/AD5340/AD5341 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin allows the output range to be set at 0 V to VREF
or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0 V and remains there until
valid data is written to the device.
The AD5330/AD5331/AD5340/AD5341 are available in Thin
Shrink Small Outline Packages (TSSOP).
*. Patent Number 5,969,657; other patents pending.
AD5330/AD5331/AD5340/AD5341–SPECIFICATIONS
(VDD = 2.5 V to 5.5 V, VREF = 2 V. RL = 2 k� to GND; CL = 200 pF to GND; all speciﬁcations TMIN to TMAX unless otherwise noted.)
OUTPUT CHARACTERISTICS
POWER REQUIREMENTS
NOTESSee Terminology section.
2Temperature range: B Version: –40°C to +105°C; typical speciﬁcations are at 25°C.Linearity is tested using a reduced code range: AD5330 (Code 8 to 255); AD5331 (Code 28 to 1023); AD5340/AD5341 (Code 115 to 4095).
4DC speciﬁcations tested with output unloaded.This corresponds to x codes. x = Deadband voltage/LSB size.
6Guaranteed by design and characterization, not production tested.
AD5330/AD5331/AD5340/AD5341
AC CHARACTERISTICS1
NOTESGuaranteed by design and characterization, not production tested.All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.See Figure 1.
(VDD = 2.5 V to 5.5 V. RL = 2 k� to GND; CL = 200 pF to GND; all speciﬁcations TMIN to TMAX
unless otherwise noted.)
AD5330/AD5331/AD5340/AD5341
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5330/AD5331/AD5340/AD5341 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
VOUT to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package
Power Dissipation . . . . . . . . . . . . . . .(TJ max – TA)/θJA mW
θJA Thermal Impedance (20-Lead TSSOP) . . . . . 143°C/W
θJA Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W
θJA Thermal Impedance (20-Lead TSSOP) . . . . . . 45°C/W
θJC Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
AD5330 FUNCTIONAL BLOCK DIAGRAM
BUF
GAIN
DB7
DB0.
CLR
LDAC
VREFVDD
VOUTGND
AD5330 PIN FUNCTION DESCRIPTIONS
4VOUT
AD5330 PIN CONFIGURATION
AD5330/AD5331/AD5340/AD5341
AD5331 FUNCTIONAL BLOCK DIAGRAM
BUF
DB9
DB0.
CLR
LDAC
VREFVDD
VOUTGND
AD5331 PIN FUNCTION DESCRIPTIONS
2DB9
3VREF
4VOUT
AD5331 PIN CONFIGURATION
LDAC
GAIN
GND
DB8
VREF
VOUT
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
CLR
DB9
AD5340 FUNCTIONAL BLOCK DIAGRAM
BUF
GAIN
DB11
DB0.
CLR
LDAC
VREFVDD
VOUTGND
AD5340 PIN FUNCTION DESCRIPTIONS
AD5340 PIN CONFIGURATION
AD5330/AD5331/AD5340/AD5341
AD5341 FUNCTIONAL BLOCK DIAGRAM
VOUT
GND
VDD
HBEN
CLR
LDAC
BUF
GAIN
DB7
DB0.
VREF
AD5341 PIN FUNCTION DESCRIPTIONS
AD5341 PIN CONFIGURATION
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, Relative Accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL versus Code plot can be seen in Figures
5, 6, and 7.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A speciﬁed differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Typical DNL versus Code plot can be seen in
Figures 8, 9, and 10.
GAIN ERROR
This is a measure of the span error of the DAC (including any
error in the gain of the buffer ampliﬁer). It is the deviation in
slope of the actual DAC transfer characteristic from the ideal
expressed as a percentage of the full-scale range. This is illus-
trated in Figure 2.
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
ampliﬁer. It is expressed as a percentage of the full-scale range.
If the offset voltage is positive, the output voltage will still be
positive at zero input code. This is shown in Figure 3. Because
the DACs operate from a single supply, a negative offset cannot
appear at the output of the buffer ampliﬁer. Instead, there will
be a code close to zero at which the ampliﬁer output saturates
(ampliﬁer footroom). Below this code there will be a deadband
over which the output voltage will not change.This is illustrated
in Figure 4.
Figure 2.Gain Error
Figure 3.Positive Offset Error and Gain Error
Figure 4.Negative Offset Error and Gain Error
AD5330/AD5331/AD5340/AD5341
OFFSET ERROR DRIFT
This is a measure of the change in Offset Error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
GAIN ERROR DRIFT
This is a measure of the change in Gain Error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by changes in
the supply voltage. PSRR is the ratio of the change in VOUT to a
change in VDD for full-scale output of the DAC. It is measured
in dBs. VREF is held at 2 V and VDD is varied ±10%.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC output
to the reference input when the DAC output is not being updated
(i.e., LDAC is high). It is expressed in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-Code Transition Glitch Energy is the energy of the
impulse injected into the analog output when the DAC changes
state. It is normally speciﬁed as the area of the glitch in nV secs
and is measured when the digital code is changed by 1 LSB at
the major carry transition (011...11 to 100...00 or 100...00
to 011...11).
DIGITAL FEEDTHROUGH
Digital Feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(CS held high). It is speciﬁed in nV secs and is measured with a
full-scale change on the digital input pins, i.e., from all 0s to all
1s and vice versa.
MULTIPLYING BANDWIDTH
The ampliﬁers within the DAC have a ﬁnite bandwidth. The
Multiplying Bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The Multiplying Bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.

Partno	Mfg	Dc	Qty	Available	Descript
AD5330BRU	TI	N/a	300	avai	2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
AD5331BRU	ADI	N/a	2	avai	2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
AD5340BRU	AD	N/a	92	avai	2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs